MPC2003SG66 Ver la hoja de datos (PDF) - Motorola => Freescale
Número de pieza
componentes Descripción
Fabricante
MPC2003SG66
Motorola => Freescale
MPC2003SG66 Datasheet PDF : 14 Pages
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BAA
K
TSC
TSP
A15 – A0
EXTERNAL
ADDRESS
ADDRESS
REGISTERS
BLOCK DIAGRAM (See Note)
BURST LOGIC
INTERNAL
ADDRESS
A1′
Q1
BINARY
16
COUNTER
LOAD
Q0 A0′
D1
D0
A1
A0
A15 – A2
16
64K x 18
MEMORY
ARRAY
WRITE
UW
REGISTER
LW
18
99
DATA–IN
REGISTERS
E
G
DQ0 – DQ8
9
DQ9 – DQ17
9
ENABLE
REGISTER
99
OUTPUT
BUFFER
NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the se-
cond cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is ad-
vanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE GRAPH. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE GRAPH (See Note)
0,0
A1′, A0′ = 1,1
0,1
1,0
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence graph. The burst logic ad-
vances A1 and A0 as shown above.
MOTOROLA FAST SRAM
MPC2002•MPC2003
5
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