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MN838898

CMOS LSI source driver for color TFT LCD panels

Panasonic Corporation 

MN838898

6.8 Relationship between Input Data and Output Voltage

6.8.1 Built-In Gamma Adjustment Resistors

The output voltage depends on the input data and thirteen gamma adjustment voltages

(VREF x, x = H, 0 to 10, L). See graph and conversion table on the next two pages.

VREF0

VREF1

VREF2

Inside LSI

R0

R1

The LSI contains ten divider resistances and two switches

between VREGF0 and VREGF10. Table 6.8 summarizes the

formulas for calculating the output voltages from the

voltages applied to pins VREF x, x = 0 to 10. Applying

voltages only to VREF0 and VREF10 produces the default

graph shown in Figure 6.8.2.

Note that we recommend the use of an operational

amplifier or similar means to guarantee low-impedance

input to the VREF pins.

Direct input sometimes fails to produce the desired output

voltages.

VREF3

R2

VREF4

VREF5

(Note 1)

R3

The adjustment voltages (VREF x, x = H, 0 to 10) must

satisfy one of the following two relationships.

R4

AVDD > VREF0 ≥ VREF1 ≥ VREF2 ≥ ・・・・

or

・・・・ ≥ VREF9 ≥ VREFL10 > AVSS

VREF6

VREF7

R5

AVDD > VREF10≥ VREF9 ≥ VREF8 ≥ ・・・・

・・・・ ≥ VREF1 ≥ VREF0 > AVSS

Do not change these voltages while the chip is in

R6

operation.

VREF8

R7

The following are the values for the internal resistances

R0 to R9 for R2=1.0.

Gamma Adjustment Resistances

VREF9

R8

VREF10

R9

Figure 6.8.1

Built-In Gamma Adjustment Resistors

R0　　　

1.15

R1　　　

1.09

R2　　　

1.00

R3　　　

1.00

R4　　　

1.00

R5　　　

1.00

R6　　　

1.00

R7　　　

1.00

R8　　　

1.09

R9　　　

1.15

SDF00030AEM

9

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