CBT3384D Ver la hoja de datos (PDF) - Philips Electronics
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CBT3384D Datasheet PDF : 10 Pages
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Philips Semiconductors
10-bit bus switch with 5-bit output enables
Product data
CBT3384
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = –40 to +85 °C
Min Typ1 Max
VIK Input clamp voltage
VCC = 4.5 V; II = –18 mA
—
II
Input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
—
ICC
Quiescent supply current2
VCC = 5.5 V; IO = 0, VI = VCC or GND
—
∆ICC
Additional supply current per input pin2
VCC = 5.5 V, one input at 3.4 V, other inputs at VCC
or GND
—
— –1.2
—
±1
—
3
—
2.5
CI
Control pins
VI = 3.0 V or 0
—
4
—
CI(OFF) Port off capacitance
VO = 3.0 V or 0, OE = VCC
—
10
—
VCC = 4.5 V; VI = 0 V; II = 64 mA
—
5
7
ron3 On-resistance
VCC = 4.5 V; VI = 0 V; II = 30 mA
—
5
7
VCC = 4.5 V; VI = 2.4 V; II = –15 mA
—
10
15
VP
Pass voltage
VI = VCC = 5.0 V; IO = –100 µA
3.4
3.6
3.9
IUCP Undershoot static current protection
VCC = 5.0 V, IB = 400 µA; OE = 5.0 V; VB ≥ 3.0 V
—
8
—
NOTES:
1. All typical values are at VCC = 5 V, Tamb = 25 °C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
UNIT
V
µA
µA
mA
pF
pF
Ω
V
mA
AC CHARACTERISTICS
GND = 0 V; tR; CL = 50 pF
SYMBOL
PARAMETER
tpd
Propagation delay1
ten
Output enable time
to High and Low level
FROM
(INPUT)
A or B
OE
TO
(OUTPUT)
B or A
A or B
LIMITS
VCC = +5.0 V ±0.5 V
Min
Max
—
.25
1.0
5.7
UNIT
ns
ns
tdis
Output disable time
from High and Low level
OE
A or B
1.0
5.2
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on–state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
LIMITS
SYMBOL
PARAMETER DESCRIPTION
MIN.
Tamb = –40 to +85 °C
VCC = 5 V, ±0.5 V
MEAN
MAX.
UNIT
tpd
Propagation delay (see Note 1)
—
—
250
ps
tPZH
Output enable time to High level
1.6
3.4
5.6
ns
tPHZ
Output enable time from High level
1.7
3.3
5.5
ns
tPZL
Output enable time to Low level
2.3
4
6
ns
tPLZ
Output enable time from Low level
2.5
4.5
6.6
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance); at +25 °C.
2001 Dec 20
4
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