MM74HC423A Ver la hoja de datos (PDF) - Fairchild Semiconductor

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MM74HC423A

Dual Retriggerable Monostable Multivibrator

Fairchild Semiconductor 

Theory of Operation

FIGURE 1.

TRIGGER OPERATION

As shown in Figure 1 and the Logic Diagram before an

input trigger occurs, the one-shot is in the quiescent state

with the Q output LOW, and the timing capacitor CEXT com-

pletely charged to VCC. When the trigger input A goes from

VCC to GND (while inputs B and clear are held to VCC) a

valid trigger is recognized, which turns on comparator C1

and N-Channel transistor N11. At the same time the output

latch is set. With transistor N1 on, the capacitor CEXT rap-

idly discharges toward GND until VREF1 is reached. At this

point the output of comparator C1 changes state and tran-

sistor N1 turns OFF. Comparator C1 then turns OFF while

at the same time comparator C2 turns on. With transistor

N1 OFF, the capacitor CEXT begins to charge through the

timing resistor, REXT, toward VCC. When the voltage across

CEXTequals VREF2, comparator C2 changes state causing

the output latch to reset (Q goes LOW) while at the same

time disabling comparator C2. This ends the timing cycle

with the one-shot in the quiescent state, waiting for the next

trigger.

A valid trigger is also recognized when trigger input B goes

from GND to VCC (while input A is at GND and input clear

is at VCC2.)

It should be noted that in the quiescent state CEXTis fully

charged to VCC causing the current through resistor REXT

to be zero. Both comparators are “OFF” with the total

device current due only to reverse junction leakages. An

added feature of the MM74HC423A is that the output latch

is set via the input trigger without regard to the capacitor

voltage. Thus, propagation delay from trigger to Q is inde-

pendent of the value of CEXT, REXT, or the duty cycle of the

input waveform.

RETRIGGER OPERATION

The MM74HC423A is retriggered if a valid trigger occurs 3

followed by another trigger 4 before the Q output has

returned to the quiescent (zero) state. Any retrigger, after

the timing node voltage at pin or has begun to rise from

VREF1, but has not yet reached VREF2, will cause an

increase in output pulse width T. When a valid retrigger is

initiated 4, the voltage at the R/CEXT pin will again drop to

VREF1 before progressing along the RC charging curve

toward VCC. The Q output will remain high until time T, after

the last valid retrigger.

Because the trigger-control circuit flip-flop resets shortly

after CX has discharged to the reference voltage of the

lower reference circuit, the minimum retrigger time, trr is a

function of internal propagation delays and the discharge

time of CX:

Another removal/retrigger time occurs when a short clear

pulse is used. Upon receipt of a clear, the one shot must

charge the capacitor up to the upper trip point before the

one shot is ready to receive the next trigger. This time is

dependent on the capacitor used and is approximately:

3

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