EM19110 Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM19110 Datasheet PDF : 6 Pages
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EM19110
10-BIT 5 MSPS A/D CONVERTER
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
with the following rising edge. The delay from the clock rising edge to the data output is the output data delay
about 20ns.
6. /OE
By connecting /OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
7. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up
due to the voltage difference between AVDD and DVDD pins when power is ON.
8. Tap reference voltage
Tap reference voltage VR1 thru VR3 connect to eighth point along the reference ladder; VR1 is 1/4th up from
VRB, VR2 is 2/4th up from VRB, VR3 is 3/4th up from VRB. These pins connecting 0.1uF capacitor to VSS
can stabilize the transfer characteristic. By connecting these pins to voltage sources, the piece wise linear
transfer curve can be attained.
* This specification are subject to be changed without notice.
5.26.1997 5
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