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ML9226

32-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan

Oki Electric Industry 

OKI Semiconductor

FEDL9226-01

ML9226

PIN DESCRIPTIONS

Pin

1, 64

10

33

30

41

50 to 63,

65 to 67,

69 to 71,

73, 74

75, 76,

78 to 80,

2 to 6

7, 8, 9

36

35

34

27

29

42 to 49

21 to 26

16 to 20

11 to 15

Symbol

VDISP

D-GND

L-GND

VCC

VREG

SEG1 to 22

SEG23 to 32

GRID1 to 3

CS

CLOCK

DATA I/O

INT

DUP/TRI

CH1 to 8

A1 to A3

B1 to B3

COL1 to 5

ROW1 to 5

Type

—

—

—

O

O

Description

Power supply pins.

Pin1 and pin64 should be connected externally.

D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for

the logic circuit. Pins 10 and 33 should be connected externally.

5 V output pin for internal logic portion and external logic circuit.

Reference voltage (5 V) output pin for A/D converter.

Segment (anode) signal output pins for a VFD tube.

O These pins can be directly connected to the VFD tube. External circuit is

not required. IOH ≤ –5 mA

Segment (anode) signal output pins for a VFD tube.

O These pins can be directly connected to the VFD tube. External circuit is

not required. IOH ≤ –10 mA

Inverted Grid signal output pins.

O

For pre-driver, the external circuit is requiend. IOL ≤ 10 mA

Chip Select input pin.

I

Data input/output operation is valid when this pin is set at a High level.

Serial clock input pin.

I Data is input and/or output through the DATA I/O pin at the rising edge of

the serial clock.

Serial data input/output pin.

I/O Data is input to/comes out from the shift register at the rising edge of the

serial clock.

Interrupt signal output to microcontroller. When any key of key matrix is

O pressed or released, key scanning is started. After the completion of the

one cycle, this pin goes to high level and keeps the high level until

keyscan stop mode is selected.

Duplex/Triplex operation select input pin.

I Duplex (1/2 duty) operation is selected when this pin is set at a VCC level.

Triplex (1/3 duty) operation is selected when this pin is set at a GND level.

I Analog voltage input pin for the 8-bit A/D converter.

I

Input pin for the encoder type rotary switch. The phase of an An/Bn input

is detected.

Return inputs from the key matrix.

I

These pins are active low. When key matrix are in the inactive sate, these

pins are at high level through the internal pull-up resistors. All the inputs

do not have the cahttering absorption function for the keyscans.

Key switch scanning outputs.

Normally low level is output through these pin. When any switch of key

O matrix is depressed or released, key scanning is started and is continued

until keyscan stop mode is selected. When keyscan stop mode is

selected, all outputs of ROW1 to 5 go back to low level.

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