ML674001 Ver la hoja de datos (PDF) - Oki Electric Industry
Número de pieza
componentes Descripción
Fabricante
ML674001 Datasheet PDF : 24 Pages
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OKI Semiconductor
FEDL674001-01
ML674001/67Q4002/67Q4003
PIN DESCRIPTION
Pin Name
I/O
Description
System
RESET_N
BSEL[1:0]
OSC0
I Reset input
I Boot device select signal
BSEL[1] BSEL[0] Boot device
0
0
Internal Flash (External ROM for ML674001)
0
1
External ROM
1
*
Boot mode
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF)
after reset.
I Crystal connection or external clock input.
Connect a crystal (16 MHz to 33 MHz), if used, to OSC0 and OSC1_N.
It is also possible to input a direct clock.
OSC1_N
O Crystal connection.
When not using a crystal, leave this pin unconnected.
CKO
O
CKOE_N
I
Debugging support.
TCK
I
TMS
I
nTRST
I
TDI
I
TDO
O
Clock out
Clock out enable
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally leave open.
General-purpose I/O ports
PIOA[7:0]
I/O General-purpose port.
Not available for use as port pins when secondary functions are in use.
PIOB[7:0]
I/O General-purpose port.
Not available for use as port pins when secondary functions are in use.
PIOC[7:0]
I/O General-purpose port.
Not available for use as port pins when secondary functions are in use.
PIOD[7:0]
I/O General-purpose port.
Not available for use as port pins when secondary functions are in use.
Note that enabling DRAM controller with DRAME_N inputs permanently
configures PIOD[7:0] for their secondary functions, making them
unavailable for use as port pins.
PIOE[9:0]
I/O General-purpose port.
Not available for use as port pins when secondary functions are in use.
Primary/
Secondary
Logic
—
Negative
—
Positive
—
—
—
—
—
—
—
Negative
—
—
—
Positive
—
Negative
—
Positive
—
Positive
Primary
Primary
Primary
Primary
Positive
Positive
Positive
Positive
Primary
Positive
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