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ML674000 Ver la hoja de datos (PDF) - Oki Electric Industry

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ML674000 Datasheet PDF : 24 Pages
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OKI Semiconductor
FEDL674000-02
ML674000
Pin Name I/O
Description
External Bus
XA[23:19]
Address bus to external RAM, external ROM, external I/O banks, and
O external DRAM. After a reset, these pins are configured for their primary
function (PIOA[14:10]).
XA[18:0]
Address bus to external RAM, external ROM, external I/O banks, and
O external DRAM
XD[15:0]
Data bus to external RAM, external ROM, external I/O banks, and external
I/O DRAM
External bus control signals
XROMCS_N
O ROM bank chip select
XRAMCS_N
O SRAM bank chip select
XIOCS_N[0]
O I/O bank 0 chip select
XIOCS_N[1]
O I/O bank 1 chip select
XOE_N
O Output enable/read enable
XWE_N
O Write enable
XBS_N[1:0]
O Byte select: XBS_N[1] for MSB; XBS_N[0] for LSB
XBWE_N[0]
O LSB write enable
XBWE_N[1]
O MSB write enable
XWR
Data transfer direction for external bus, used when connecting to Motorola
O I/O devices. This represents the secondary function of pin PIOA[15],
produced by setting bit 7 in the port control (GPCTL) register to "1."
XWAIT
External I/O bank 0 WAIT signal.
I This input permits access to devices slower than register settings.
External bus control signals (DRAM)
XRAS_N
O Row address strobe. Used for both EDO DRAM and SDRAM.
XCAS_N
O Column address strobe signal (SDRAM)
XSDCLK
O SDRAM clock (same frequency as internal system clock)
XSDCKE
O Clock enable (SDRAM)
XSDCS_N
O Chip select (SDRAM)
XDQM[1]/
XCAS_N[1]
Connected to SDRAM: DQM (MSB)
O
Connected to EDO DRAM: column address strobe signal (MSB)
XDQM[0]/
XCAS_N[0]
O Connected to SDRAM: DQM (LSB)
Connected to EDO DRAM: column address strobe signal (LSB)
Primary/ Logic
Secondary
Secondary Positive
Positive
Positive
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Secondary
Secondary Positive
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Negative
Negative
Negative
Positive/
Negative
Positive/
Negative
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