ML6651 Ver la hoja de datos (PDF) - Micro Linear Corporation

Número de pieza

componentes Descripción

Fabricante

ML6651

Auto-Negotiating Media Converter

Micro Linear Corporation 

ADVANCED

ML6651

PIN DESCRIPTIONS (continued)

Pin # Signal Name Description

29

SDFO

Fiber Optic Interface Mode:

This pin is not used and should be connected to any potential between VCC and Ground.

LVPECL/PECL Compatible Interface Mode:

This input pin is connected to the Signal Detect (SD) output of a fiber optic PMD. The voltage

level at this pin is compared to the voltage level at pin SDTH to determine the logic value.

39

SDTH

The voltage at this pin is a single ended LVPECL/PECL reference. Refer to description of SDFO

and REQSD pins.

This pin is not used if either the TPINP/TPINN interface, or the FOINP/FOINN are setup for

LVPECL/PECL compatible mode. In such a case, the SDTH pin must be connected to any

potential between VCC and Ground.

41

TPINSPD This output pulls up to indicate that 100Mb/s signal is present at the TPINP/TPINN interface, and

it pulls down to indicates that 10Mb/s signal is present at the TPINP/TPINN interface. The signal

can be idle or packets. This pin is set to high impedance otherwise. This pin can also be

configured as a test output (see Test Outputs).

42 FOINSPD This output pulls up to indicate that 100Mb/s signal is present at the FOINP/FOINN interface,

and it pulls down to indicates that 10Mb/s signal is present at the FOINP/FOINN interface. The

signal can be idle or packets. This pin is set to high impedance otherwise. This pin can also be

configured as a test output (see Test Outputs).

43

TPANDT When TPINSPD is in the high impedance state, no 10 or 100Mbs signal at TPINP/TPINN, the

TPANDT LED pulls low while receiving Auto-Negotiation signal at the TPINP/TPINN interface.

When TPINSPD is not in the high impedance state, the TPANDTpin pulls low to indicate that a

data packet is being detected at the TPINP/TPINN interface. When a data packet is indicated,

the pulse width at TPANDT is stretch to a minimum of 1.3 to 2.7ms to improve visibility (or

163ms to 328ms, when the TestFast bit 28.0 is 1).

This pin can also be configured as a test output (see Test Outputs).

In any other case this pin is in high impedance state.

44 FOANDT When FOINSPD is in the high impedance state, no 10 or 100 Mb/s signal at FOINP/FOINN, the

FOANDT LED pulls low while receiving Auto-Negotiation signal at the FOINP/FOINN

interface.

When FOINSPD is not in the high impedance state, the FOANDT pin pulls low to indicate that

a data packet is being detected at the FOINP/FOINN interface. When a data packet is

indicated, the pulse width at FOANDT is stretch to a minimum of 1.3 to 2.7ms to improve

visibility (or 163ms to 328ms, when the TestFast bit 28.0 is 1).

This pin can also be configured as a test output (see Test Outputs).

In any other case this pin is in high impedance state.

40 BCKPLINK When the Backup Link function is enabled, this pin is the enabler of a secondary link. Connect

to VCC to disable this function. Pull down to ground to enable this function. Recommended pull

down resistor value: 10KW.

7

PECLTP

This pin sets the Media Converter to interface at pins TPINP/TPINN and TPOUTP/TPOUTN, to an

external PECL or LVPECL PMD, or to twisted pair interface magnetics. When PECL or LVPECL

interface is selected, the 100Mb/s scrambler and descrambler functions are disabled by default

and can be enabled with a management register bit. When twisted pair interface is selected,

the scrambler and descrambler are enabled by default and can be disabled with a management

register bit.

When using twisted pair interface, this pin also indicates the maximum supported link distance.

When the 10m maximum link length is selected, the input is not equalized before being sliced.

September 2000 Advanced Datasheet

7

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