ML6651 Ver la hoja de datos (PDF) - Micro Linear Corporation

Número de pieza

componentes Descripción

Fabricante

ML6651

Auto-Negotiating Media Converter

Micro Linear Corporation 

ADVANCED

ML6651

PIN DESCRIPTIONS (continued)

Pin # Signal Name Description

22

IOUT

Fiber Optic Interface Mode:

IOUT (pin 21) is the Fiber optic LED driver output while pin IOUT (pin 22) is optionally used to

provide current peaking. IOUT connects to the cathode of an external LED. It drives NRZI

encoded 100BASE-FX or 100BASE-SX symbols during 100Mb/s mode, Manchester encoded

10BASE-FL data or OPTIDL during 10Mb/s mode, and FLNP Bursts during Auto-Negotiation.

When peaking is not used, IOUT should connect to VCC. When peaking is used, an off-chip

resistor from this pin to ground and an off-chip capacitor from this pin to IOUT determine the

peaking current waveform. (Typical values are 1KW and 1nF)

LVPECL / PECL Compatible Interface Mode:

LVPECL or PECL interface positive and complementary outputs. These outputs form a differential

current output pair that drives NRZI encoded 100BASE-SX or 100BASE-FX symbols during

100Mb/s mode, Manchester encoded 10BASE-FL data or OPTIDL during 10Mb/s mode, and

FLNP Bursts during Auto-Negotiation. IOUT and IOUT are loaded with external resistors to VCC

and AC coupled to the inputs of a 1x9 fiber optic PMD module. A resistor network may be

needed to setup the common mode voltage at the input pins of the PMD module.

36

RTOP

Fiber optic LED or LVPECL/PECL driver bias resistor. An external resistor connected between

RTOP and ground sets a constant bias current for the single ended LED driver or differential

LVPECL/PECL driver circuitry. These output currents depend on the operating mode.

The recommended external component values are:

Fiber Optic Interface mode: (1% resistors, +/- 10% currents)

Indicated is the current into pin IOUT during the High-Light state.

2.8KW between RTOP and ground for 50mA.

2KW between RTOP and ground for 70mA.

1.4KW between RTOP and ground for 100mA.

LVPECL Interface mode:

1.4KW, 1 %, between RTOP and ground for 10mA tail current.

62W , 1 %, between IOUT and VCC.

62W 1 %, between IOUT and VCC.

Also AC couple to PMD inputs.

33

FOINP

2 operating modes are available for these pins and are selected with the configuration pin

PECLQU or the configuration bit LVPECLQU (bit 30.7).

32

FOINN

Fiber Optic Interface Mode:

Fiber optic quantizer positive and complementary inputs. FOINP is capacitively coupled to the

output of a fiber optic receiver, while FOINN is capacitively coupled to the VCC of the fiber

optic receiver. Recommended capacitor values: 10nF, 5%. FOINP voltage must be higher

during the “high light” state than during the low-light state.

LVPECL/PECL Compatible Interface Mode:

LVPECL/PECL interface positive and complementary inputs. These inputs form a differential

input pair that receives 100BASE-FX, 100BASE-SX, FLNP Bursts, or 10BASE-FL signal from a

fiber optic PMD. The PMD outputs are AC coupled to these inputs with .1mF capacitors. The

common mode voltage is set internally with resistors of about 500W from each input pin to an

on-chip voltage reference. FOINP voltage must be higher during the “high light” state than

during the low-light state.

30

CQOS

Fiber Optic Interface Mode:

Data quantizer offset cancellation loop capacitor. An external capacitor between this pin and

VCC determines the dominant pole of the offset cancellation feedback look. The recommended

value is .1mF, 10 %.

LVPECL/PECL Compatible Interface Mode:

This pin is not used and should be left unconnected.

6

Advanced Datasheet September 2000

Share Link: