ML6426CS-3 Ver la hoja de datos (PDF) - Micro Linear Corporation

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Fabricante

ML6426CS-3

High Bandwidth Triple Video Filters with Buffered Outputs for RGB or YUV

Micro Linear Corporation 

ML6426

PIN CONFIGURATION

ML6426

16-Pin Narrow SOIC (S16N)

A/B MUX

RINA/YINA

GND

VCC

RINB/YINB

GINA/UINA

GINB/UINB

BINA/VINA

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

TOP VIEW

SYNC IN

DISABLE

GNDO

ROUT/YOUT

VCCO

GOUT/UOUT

BOUT/VOUT

BINB/VINB

PIN DESCRIPTION

PIN NAME

FUNCTION

1 A/B MUX Logic input pin to select between

Bank <A> and Bank <B> video inputs.

This pin is internally pulled high.

2 RINA/YINA Unfiltered analog R- or Y-channel

input for Bank <A>. Sync must be

provided at SYNC IN pin.

3 GND

Analog ground

4 VCC

Analog 5V supply

5 RINB/YINB Unfiltered analog R- or Y-channel

input for Bank <B>. Sync must be

provided at SYNC IN pin.

6 GINA/UINA Unfiltered analog G- or U-channel

input for Bank <A>. Sync must be

provided at SYNC IN pin.

7 GINB/UINB Unfiltered analog G- or U-channel

input for Bank <B>. Sync must be

provided at SYNC IN pin.

PIN NAME

FUNCTION

8 BINA/VINA Unfiltered analog B- or V-channel

input for Bank <A>. Sync must be

provided at SYNC IN pin.

9 BINB/VINB Unfiltered analog B- or V-channel

input for Bank <B>. Sync must be

provided at SYNC IN pin.

10 BOUT

11 GOUT

12 VCCO

13 ROUT

14 GNDO

Analog B or V-channel output

Analog G or U-channel output

5V power supply for output buffers

Analog R or Y-channel output

Analog ground

15 DISABLE Disable/Enable pin. Turns the chip off

when logic high. Internally pulled low.

16 SYNC IN

Input for an external H-sync logic

signal for filter channels. CMOS

level input. Active High.

2

November, 1999

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