ML6426CS4X_NL Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

ML6426CS4X_NL

High Bandwidth Triple Video Filters with Buffered Outputs for RGB or YUV

Fairchild Semiconductor 

ML6426

Pin Configuration

ML6426

16-Pin Narrow SOIC (S16N)

A/B MUX

RINA/YINA

GND

VCC

RINB/YINB

GINA/UINA

GINB/UINB

BINA/VINA

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

TOP VIEW

SYNC IN

DISABLE

GNDO

ROUT/YOUT

VCCO

GOUT/UOUT

BOUT/VOUT

BINB/VINB

DATA SHEET

Pin Description

PIN NAME

1 A/B MUX

2

RINA/YINA

3 GND

4

VCC

5

RINB/YINB

6

GINA/UINA

7

GINB/UINB

8

BINA/VINA

9

BINB/VINB

10 BOUT

11 GOUT

12 VCCO

13 ROUT

14 GNDO

15 DISABLE

16 SYNC IN

FUNCTION

Logic input pin to select between Bank <A> and Bank <B> video inputs. This pin is

internally pulled high.

Unfiltered analog R- or Y-channel input for Bank <A>. Sync must be provided at

SYNC IN pin.

Analog ground

Analog 5V supply

Unfiltered analog R- or Y-channel input for Bank <B>. Sync must be provided at

SYNC IN pin.

Unfiltered analog G- or U-channel input for Bank <A>. Sync must be provided at

SYNC IN pin.

Unfiltered analog G- or U-channel input for Bank <B>. Sync must be provided at

SYNC IN pin.

Unfiltered analog B- or V-channel input for Bank <A>. Sync must be provided at

SYNC IN pin.

Unfiltered analog B- or V-channel input for Bank <B>. Sync must be provided at

SYNC IN pin.

Analog B or V-channel output

Analog G or U-channel output

5V power supply for output buffers

Analog R or Y-channel output

Analog ground

Disable/Enable pin. Turns the chip off when logic high. Internally pulled low.

Input for an external H-sync logic signal for filter channels. CMOS level input.

Active High.

2

REV. 3A August 2004

Share Link: