CXA1977R Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXA1977R Datasheet PDF : 16 Pages
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CXA1977R
Item
Digital output
Symbol Measurement conditions
Min.
VOH
Digital output voltage
VOL
Leak current during output off IOZ
Dynamic characteristics
IOH = –300µA
2.7
DVCC1, 2 = 4.6V
IOL = +500µA
DVCC1, 2 = 5.25V, VO = 3.6V
–20
Differential gain error
Differential phase error
DG
NTSC 40IRE mod. ramp,
DP
Fc = 14.3MSPS
SNR
SNR
Fc = 20MSPS FIN = 1kHz
Fc = 20MSPS FIN = 1MHz
Fc = 20MSPS FIN = 2MHz
Fc = 20MSPS FIN = 7.5MHz
Power supply
DVCC1 current
DVCC2 current
DVCC3 current
AVCC current
Power dissipation Pd = A + B
A = (IDVCC1 + IDVCC2 + IDVCC3
+ IAVCC) × 5V
B = | IREF | × 2V
IDVCC1
IDVCC2
IDVCC3
IAVCC
Pd
DVCC1 = +5V
∗8 During power save
DVCC2 = +5V
∗8 During power save
DVCC3 = +5V
∗8 During power save
AVCC = +5V
∗8 During power save
∗8 During power save
6.0
4.3
0.05
0
8.1
0.34
0.5
0
87
37
∗1 +1 < EDL2 ≤ +2 (LSB) is two and under.
∗2 CLK input
∗3 MINV, LINV, ENABLE, and PS inputs
∗4 Refer to Timing Diagram (1)
∗5 Refer to Timing Diagram (2)
∗6 The load is a bi-state totem-pole output delay time test load circuit.
∗7 The load is a 3-state output test load circuit.
∗8 When PS and ENABLE inputs are in high level.
Typ.
3.4
0.5
0.3
55
53
52
49
9.9
7.3
0.16
0
14.7
0.55
3.2
20
160
59
Max. Unit
V
0.5 V
75 µA
%
deg
dB
dB
dB
dB
14.0 mA
12.0 mA
0.30 mA
27 mA
21.1 mA
1.13 mA
6.0 mA
50 µA
239 mW
98 mW
–7–
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