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ML4833CS

Electronic Dimming Ballast Controller

Micro Linear Corporation 

ML4833

FUNCTIONAL DESCRIPTION

OVERVIEW

The ML4833 consists of peak current controlled

continuous boost power factor front end section with a

flexible ballast control section. Start-up and lamp-out

retry timing are controlled by the selection of external

timing components, allowing for control of a wide variety

of different lamp types. The ballast section controls the

lamp power using frequency modulation (FM) with

additional programmability provided to adjust the VCO

frequency range. This allows for the IC to be used with a

variety of different output networks. Figure 1 depicts a

detailed block diagram of ML4833.

POWER FACTOR SECTION

The ML4833 power factor section is a peak current

sensing boost mode PFC control circuit in which only

voltage loop compensation is needed. It is simpler than a

conventional average current control method. It consists

of a voltage error amplifier, a current sense amplifier (no

compensation is needed), an integrator, a comparator, and

a logic control block. In the boost topology, power factor

correction is achieved by sensing the output voltage and

the current flowing through the current sense resistor. Duty

cycle control is achieved by comparing the integrated

voltage signal of the error amplifier and the voltage

across RSENSE. The duty cycle control timing is shown in

Figure 2. Setting minimum input voltage for output

regulation can be achieved by selecting CRAMP according

to equation 1.

{ } CRAMP

=

PEAOMAX

22K

(1− D)Ts − 1.1µs







1

2POUT

VIN

−





VOUT

−

2L

2VIN





(1−



D)Ts



8RSENSE

(1)

OVERVOLTAGE PROTECTION AND INHIBIT

The OVP pin serves to protect the power circuit from

being subjected to excessive voltages if the load should

change suddenly (lamp removal). A divider from the high

voltage DC bus sets the OVP trip level. When the voltage

on PVFB/OVP exceeds 2.75V, the PFC transistor are

inhibited. The ballast section will continue to operate.

RSET

6

RT/CT

7

RX/CX

9

VCC

16

VREF

17

UNDER-VOLTAGE

THERMAL SHUTDOWN

REFOK

GND

11

2.5V +

PVFB/OVP

18

–

PEAO

1

CRAMP

10

PREHEAT

TIMER

V TO I

OSC

CLK

+

1.25V

–

SQ

–

R

+

– OVP

2.75V +

PIFB

2

–1.0V – ILIM

+

SQ

R

ISENSE AMPLIFIER

TQ

LFB OUT

5

+ 2.5V

LAMP FB

–

4

INTERRUPT

8

PDWN

+

3

– 1.0V

PFC OUT

15

OUT A

14

OUT B

13

PGND

12

Figure 1. ML4833 Detailed Block Diagram

6

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