MK2771-15 Ver la hoja de datos (PDF) - Integrated Circuit Systems

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MK2771-15

VCXO and Set-Top Clock Source

Integrated Circuit Systems 

MK2771-15

VCXO and Set-Top Clock Source

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Minimum Typical Maximum Units

Supply voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Referenced to GND

-0.5

Ambient Operating Temperature

0

Soldering Temperature

Max of 10 seconds

Storage temperature

-65

DC CHARACTERISTICS (VDD, VDDIO = 5.0V unless noted)

7

V

VDDIO+0.5 V

70

°C

260

°C

150

°C

Operating Voltage, VDD

4.75

Operating Voltage, VDDIO

for all inputs/outputs

3.15

Input High Voltage, VIH, X1 pin only

3.5

Input Low Voltage, VIL, X1 pin only

Input High Voltage, VIH (except SC & PCS2)

2

Input Low Voltage, VIL (except SC & PCS2)

Input High Voltage, VIH, SC & PCS2 only

VDDIO-0.5

Input Low Voltage, VIL, SC & PCS2 only

Output High Voltage, VOH

IOH=-25mA

2.4

Output Low Voltage, VOL

IOL=25mA

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDDIO-0.4

Operating Supply Current, IDD+IDDIO (3.3V) No Load, note 2

Short Circuit Current

Each output

Input Capacitance

Except X1, X2

Frequency synthesis error

All clocks

VIN, VCXO control voltage

0

AC CHARACTERISTICS (VDD, VDDIO = 5.0V unless noted)

2.5

2.5

46+27

±100

7

5.25

V

5.25

V

V

1.5

V

V

0.8

V

V

0.5

V

V

0.4

V

V

mA

mA

pF

0

ppm

3

V

Input Frequency

13.500000

MHz

Output Clock Rise Time

0.8 to 2.0V, no load

1.5

ns

Output Clock Fall Time

2.0 to 0.8V, no load

1.5

ns

Output Clock Duty Cycle

At VDDIO/2

40

50

60

%

Maximum Absolute Jitter, short term

300

ps

VCXO Pullability

Note 3

-100

100

ppm

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. With PCLK at 100 MHz.

3. With a pullable crystal that conforms to ICS’ specifications

External Components

The MK2771-15 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between VDD (or VDDIO) and GND on pins 5 and 24, 7 and

10, 22 and 19, and 21 and 18, as close to the MK2771-15 as possible. VDD on pin 8 can be connected

directly to the VDD on pin 21. A series termination resistor of 33 Ω may be used for each clock

output.The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a

parallel mode, pullable, with load capacitance of 14 pF. Consult ICS/MicroClock for recommended

suppliers. See MAN05 for recommended layout of the chip and external components.

MDS 2771-15 E

3

Revision 122899

Printed 11/16/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com

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