MK2771-15 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2771-15 Datasheet PDF : 4 Pages
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MK2771-15
VCXO and Set-Top Clock Source
Pin Assignment
PCS0 1
X2 2
X1 3
VDD 4
VDD 5
VIN 6
VDDIO 7
VDD 8
SC 9
GND 10
PCLK1 11
PCLK2 12
PCS1 13
ACLK 14
28 ACS1
27 ACS0
26 54M
25 27M
24 GND
23 CCLK1
22 VDD
21 VDD
20 PCS2
19 GND
18 GND
17 CCLK2
16 13.5M
15 DC
Pin Descriptions
Processor Clock Select Table (MHz)
PCS2
0
0
0
0
1
1
1
1
PCS1
0
0
1
1
0
0
1
1
PCS0
0
1
0
1
0
1
0
1
PCLK1
27.500
33.333
33.326
50.000
32.400
40.000
TEST
TEST
PCLK2
Off
66.666
83.314
100.000
81.000
33.333
TEST
TEST
Audio Clock Table Comm Clock Table (MHz)
ACS1 ACS0 ACLK (MHz)
00
8.192
01
11.2896
10
12.288
11
18.432
SC CCLK1
0
18.432
M 11.0592
1 11.0592
CCLK2
24.576
18.432
24.576
0 = connect directly to ground, 1 = connect directly
to VDDIO, M = leave floating or unconnected
Number
1
2
3
4, 5, 8
6
7
9
10, 18, 19, 24
11
12
13
14
15
16
17
20
21, 22
23
25
26
27
28
Name
PCS0
X2
X1
VDD
VIN
VDDIO
SC
GND
PCLK1
PCLK2
PCS1
ACLK
DC
13.5M
CCLK2
PCS2
VDD
CCLK1
27M
54M
ACS0
ACS1
Type
I
XO
XI
P
I
P
TI
P
O
O
I
O
-
O
O
I
P
O
O
O
I
I
Description
Processor Clock Select 0. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to +3.3V or +5V. Amplitude of inputs must, and outputs will, match this.
Communications clock select pin. Biased to M level if floating.
Connect to ground.
Processor Clock output number 1. Determined by status of PCS2:0
Processor Clock output number 2. Determined by status of PCS2:0
Processor Clock Select 1. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Audio Clock Output. Determined by status of ACS1, ACS0 per table above.
Don't Connect anything to this pin.
13.50 MHz VCXO clock output.
Communications Clock Output 2 determined by status of SC per table above.
Processor Clock Select 2. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Connect to +5V.
Communications Clock Output 1 determined by status of SC per table above.
27.00 MHz VCXO clock output.
54.00 MHz VCXO clock output.
Audio Clock Select 0. Selects ACLK on pin 14. See table above. Internal pull-up.
Audio Clock Select 1. Selects ACLK on pin 14. See table above. Internal pull-up.
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
MDS 2771-15 E
2
Revision 122899
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
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