MK2722-01S Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2722-01S Datasheet PDF : 4 Pages
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MK2722
Sigma Designs Clock Source
Pin Assignment
VDD 1
X2 2
X1 3
VDD 4
GND 5
BS1 6
ACLK 7
AS0 8
16 BS0
15 PD
14 27M
13 VDD
12 AS1
11 GND
10 BCLK/2
9 BCLK
16 pin narrow (150 mil) SOIC
ACLK Decoding Table (MHz)
AS1
pin 12
0
0
0
1
1
1
AS0
pin 8
0
M
1
0
M
1
ACLK
pin 7
12.288
18.432
16.9344
11.2896
12.288
8.192
BCLK Decoding Table (MHz)
BS1
pin 6
0
0
1
1
BS0
pin 16
0
1
0
1
BCLK
pin 9
40.5
50
28.6364
40
BCLK/2
pin 10
20.25
25
14.3182
20
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VDD
X2
X1
VDD
GND
BS1
ACLK
AS0
BCLK
BCLK/2
GND
AS1
VDD
27M
PD
BS0
Type
I
XO
XI
P
P
I
O
TI
O
O
P
I
P
O
I
I
Description
Connect to +5V.
Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input.
Crystal connection. Connect to 27 MHz crystal or clock.
Connect to +5V.
Connect to ground.
Select 1 for BCLK. Determines BCLK outputs per table above. Internal pull-up.
Audio Clock output. Determined by status of AS1, AS0 per table above.
Select 0 for ACLK. Determines ACLK output per table above.
BCLK output. Determined by status of BS1, BS0 per table above.
BCLK divided by two output. Determined by status of BS1, BS0 per table above.
Connect to ground.
Select 1 for ACLK. Determines ACLK output per table above. Internal pull-up.
Connect to +5V.
27.0000 MHz buffered crystal clock output.
Power Down. Active low. Clocks stop low. Internal pull-up.
Select 0 for BCLK. Determines BCLK outputs per table above. Internal pull-up.
Key: I = Input, TI = Tri-level input, O = output, P = power supply connection
MDS 2722 B
2
Revision 020802
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295 9800tel • www.icst.com
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