MK1443-02S Ver la hoja de datos (PDF) - Integrated Circuit Systems

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MK1443-02S

SCSI and Ethernet Clock Source

Integrated Circuit Systems 

MK1442/MK1443

SCSI and Ethernet Clock Source

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Minimum Typical Maximum Units

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5 V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 20 seconds

260

°C

Storage Temperature

-65

DC CHARACTERISTICS (VDD = 5V unless noted)

150

°C

Operating Voltage, VDD

3.0

5.5

V

Input High Voltage, VIH

OE (pin 10)

2.0

V

Input Low Voltage, VIL

OE (pin 10)

0.8

V

Input High Voltage, VIH

CPUS0,1 (pins 1,16)

VDD-0.5

V

Input Mid-level Voltage

CPUS0,1 (pins 1,16) Leave pin unconnected or tri-stated

V

Input Low Voltage, VIL

CPUS0,1 (pins 1,16)

0.5

V

Output High Voltage, VOH

IOH=-4mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

Input High Voltage, VIH

VDD=3.3V, OE pin

1.9

V

Input Low Voltage, VIL

VDD=3.3V, OE pin

0.4

V

Output High Voltage, VOH

VDD=3.3V, IOH=-8mA

2.4

V

Output Low Voltage, VOL

VDD=3.3V, IOL=8mA

0.4

V

Operating Supply Current, IDD

No Load, 80 MHz

35

mA

Short Circuit Current

Each output

±100

mA

On-Chip Pull-up Resistor

250

kΩ

Input Capacitance

7

pF

Frequency Accuracy of 20.000 MHz clock

0-70°C, note 2

-1

AC CHARACTERISTICS (VDD = 5V unless noted)

1

ppm

Input Frequency

14.31818

MHz

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle, CPU and 2XCPU 1.5V, up to 67MHz

47.5

49 to 51

52.5

%

Output Clock Duty Cycle

At 1.5V

45

49 to 51

55

%

Cycle to Cycle Jitter

50-80 MHz clocks

250

ps

Skew of 2XCPU with respect to CPU

Rising edges at 1.5V

-250

0

250

ps

Transition time, 8MHz to 100MHz

VDD=3.3 or 5V

4

ms

Transition time, 100MHz to 8MHz

VDD=3.3 or 5V

2.5

ms

Output Enable Time, OE high to output on

VDD=3.3 or 5V

50

ns

Output Disable Time, OE low to tri-state

VDD=3.3 or 5V

3

µs

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. Provided proper crystal and capacitor components are used - consult MicroClock.

MDS 1442/3 E

3

Revision 111500

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 •(408)297-1201tel • www.icst.com

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