MIC2551A-2.5
Timing Diagrams
OE#
VP/VM
D+/D–
TRANSMIT
tPVZ
tPZD
RECEIVE
tPDZ
tPZV
Test Circuits
Figure 1. Enable and Disable Times
Differential
Data Lines
Rise Time
Fall Time
90%
10%
tR
90%
10%
tF
Figure 2. Rise and Fall Times
D+
VCRS
Differential
Data Lines
D–
VOH
tPLH
VOL
VSS
VCRS
tPHL
Figure 3. Receiver Propagation Delay
VOH
VOL
D+
tPLH
VCRS
Differential
Data Lines
D–
tPHL
VCRS
Figure 4. Driver Propagation Delay
D.U.T.
25pF
Figure 5. Load for VP, VM, RCV
VTRM
1.5k
D.U.T.
20
15k
CL
Figure 6. Load for D+, D–
M9999-030810
6
Micrel, Inc.
March 2010