MH8S64BBKG-10L Ver la hoja de datos (PDF) - Mitsumi
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MH8S64BBKG-10L Datasheet PDF : 55 Pages
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64BBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
FEATURES
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Frequency
-7,-7L
-8,-8L
100MHz
100MHz
-10,-10L 100MHz
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)
8.0ns(CL=3)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
PC100 compliant
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
1
(Back)
2
MIT-DS-0291-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
143
144
21.Dec.1998
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