MT90210AL Ver la hoja de datos (PDF) - Mitel Networks
Número de pieza
componentes Descripción
Fabricante
MT90210AL Datasheet PDF : 27 Pages
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Preliminary Information
MT90210
RBC
125 us
WBC
125 us
Exclusive access of
Block 0
tNA
Access
of both
Block 0
&
Block 1
Exclusive access of
Block 1
tNA
Access
of both
Block 0
&
Block 1
Exclusive access of
Block 0
tNA ~ 1 timeslot for modes 1, 2 & 3
tNA ~ 3 timeslots for modes 4 & 5
Figure 7b - WBC and RBC operation in relation to accessing data from Block 0 and Block 1
SCLK
PCLK
A0-A12
ARD ARD
AWR AWR
R/W1
R/W2
Strobe
P0-P7
RD
RD
WR
WR
Toggles only during
write data cycle
Changes state (high to low)
on every change of a block
of reads or block of writes
Low during read cycle,
high during inactive
periods and toggles
during write cycles
Note: The MT90210 device performs groups of writes and groups of reads separated by 4 inactive PCLK periods
for modes 3, 4 and 5. In mode 1 and mode 2, the write and read groups are separated by 8 PCLK periods.
Figure 8 - Parallel Port Functional Read/Write Operation
JTAG Support
The MT90210 JTAG interface is designed according
to the Boundary-Scan standard IEEE1149.1. The
standard specifies a design-for-testability technique
called Boundary-Scan Test (BST). A boundary-scan
IC has a shift-register stage or ‘Boundary-Scan Cell’
(BSC) in between the core logic and the I/O buffers
adjacent to each I/O pin. The BSCs can control and
observe what happens at each I/O pin of the IC. The
operation of the boundary-scan circuitry is controlled
by a Test Access Port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to many
test support functions built into the MT90210. It
consists of three input connections and one output
connection. The following connections form the TAP:
• Test Clock Input (TCK)
• Test Mode Select Input (TMS)
• Test Data Input (TDI)
• Test port Reset (TRST)
• Test Data Output (TDO)
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