MCP621/2/5
1.3 Timing Diagram
CAL/CS
VDD
VPRH
tPON
VIH
tCOFF
VIL
tCSU
tCON
VOUT High-Z
On
High-Z
On
VPRL
tPOFF
High-Z
ISS -3 µA (typical) -2.5 mA (typical)
-3 µA (typical)
-2.5 mA (typical)
-3 µA (typical)
ICS 0 nA (typical)
FIGURE 1-1:
Timing Diagram.
0.7 µA (typical)
0 nA (typical)
1.4 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
GDM = RF ⁄ RG
VCM = (VP + VDD ⁄ 2) ⁄ 2
VOST = VIN– – VIN+
VOUT = (VDD ⁄ 2) + (VP – VM) + VOST(1 + GDM)
Where:
GDM = Differential Mode Gain
VCM = Op Amp’s Common Mode
Input Voltage
VOST = Op Amp’s Total Input Offset
Voltage
(V/V)
(V)
(mV)
CF
6.8 pF
RG
10 kΩ
VP
VIN+
MCP62X
VIN–
VM
RG
10 kΩ
RF
10 kΩ
RF
10 kΩ
VDD
VDD/2
CB1
100 nF
CB2
2.2 µF
RL
2 kΩ
VOUT
CL
50 pF
CF
6.8 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS22188A-page 6
© 2009 Microchip Technology Inc.