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MCM69P736ZP4

128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Motorola => Freescale 

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V

Input Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%)

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V

Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted

READ/WRITE CYCLE TIMING (See Notes 1 and 2)

MCM69P736–4

133 MHz

Parameter

Symbol

Min

Max

Unit Notes

Cycle Time

Clock High Pulse Width

Clock Low Pulse Width

Clock Access Time

Output Enable to Output Valid

Clock High to Output Active

Clock High to Output Change

Output Enable to Output Active

Output Disable to Q High–Z

Clock High to Q High–Z

Setup Times:

tKHKH

7.5

tKHKL

3

tKLKH

3

tKHQV

—

tGLQV

—

tKHQX1

0

tKHQX2

1.5

tGLQX

0

tGHQZ

—

tKHQZ

1.5

Address

tADKH

1.5

ADSP, ADSC, ADV tADSKH

Data In

tDVKH

Write

tWVKH

Chip Enable

tEVKH

—

ns

—

ns

3

—

ns

3

4

ns

3.8

ns

—

ns

4, 5

—

ns

4

—

ns

4, 5

3.8

ns

4, 5

7.5

ns

4, 5

—

ns

Hold Times:

Address

tKHAX

0.5

ADSP, ADSC, ADV tKHADSX

Data In

tKHDX

Write

tKHWX

Chip Enable

tKHEX

—

ns

NOTES:

1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP

or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G.

3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between

data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some

design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is

given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.

4. This parameter is sampled and not 100% tested.

5. Measured at ± 200 mV from steady state.

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

1.25 V

Figure 2. AC Test Load

MOTOROLA FAST SRAM

MCM69P736

9

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