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MCM69F618CTQ9R Datasheet PDF : 12 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
69F618C–8.5 69F618C–9 69F618C–10 69F618C–12
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Cycle Time
tKHKH
12
—
12
—
15
— 16.6 —
ns
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
tKHKL
4
—
4
—
5
—
6
—
ns
tKLKH
4
—
4
—
5
—
6
—
ns
tKHQV
—
8.5
—
9
—
10
—
12
ns
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
tGLQV
—
5
—
5
—
5
—
6
ns
tKHQX1
0
—
0
—
0
—
0
—
ns
4
tKHQX2
3
—
3
—
3
—
3
—
ns
4
Output Enable to Output Active
Output Disable to Q High–Z
tGLQX
0
—
0
—
0
—
0
—
ns
4
tGHQZ
—
5
—
5
—
5
—
6
ns 4, 5
Clock High to Q High–Z
tKHQZ
2.5
5
3
5
3
5
3
6
ns 4, 5
Setup Times:
Address tAVKH
2.5
—
2.5
—
2.5
—
2.5
—
ns
ADSP, ADSC, ADV tADKH
Data In tDVKH
Write tWVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
—
0.5
—
ns
ADSP, ADSC, ADV tKHADX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VT = 1.5 V
Figure 1. AC Test Load
MCM69F618C
8
MOTOROLA FAST SRAM
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