MCM69D618 Ver la hoja de datos (PDF) - Motorola => Freescale
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MCM69D618 Datasheet PDF : 14 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
MCM69D618–6
MCM69D618–8
Parameter
Symbol
Min
Max
Min
Max
Unit Notes
Cycle Time
tKHKH
12
—
15
—
ns
1
Clock Access Time
tKHQV
—
6
—
8
ns
Clock Low Pulse Width
tKLKH
4
—
6
—
ns
Clock High Pulse Width
tKHKL
4
—
6
—
ns
Clock High to Data Output Active
tKHQX1
0
—
0
—
ns
Clock High to Data Output Invalid
tKHQX2
2
—
2
—
ns
Clock High to Data Output High–Z
tKHQZ
—
5
—
5
ns
2
Output Enable Low to Data Output Valid
Output Enable Low to Data Output Low–Z
tGLQV
—
6
—
8
ns
tGLQX
0
—
0
—
ns
Output Enable High to Data Output High–Z
tGHQZ
—
5
—
8
ns
2
Setup Times:
AWR0 – AWR14
tAVKH
2.5
—
3
—
ns
3
ARD0 – ARD14
tAVKH
W
tWVKH
PT tPTVKH
E1, E2
tEVKH
D0 – D35
tDVKH
Hold Times:
AWR0 – AWR14
tKHAX
0.5
—
1
—
ns
3
ARD0 – ARD14
tKHAX
3
W
tKHWX
3
PT tKHPTX
3
E1, E2
tKHEX
3
D0 – D35
tKHDX
3, 4
NOTES:
1. All read and write cycles are referenced from K.
2. This parameter is sampled and not 100% tested.
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
4. tKHDX minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising
clock edge.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM69D618
7
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