Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
MCF5274L
MCF5275L
256 MAPBGA 196 MAPBGA
External Interrupts Port
IRQ[7:5]
IRQ[4]
IRQ[3:2]
IRQ1
PIRQ[7:5]
—
—
PIRQ[4]
DREQ2
—
PIRQ[3:2] DREQ[3:2]
—
PIRQ[1]
—
—
I G13, H16, H15 F14, G13, G14
I
H14
H11
I
J14, J13
H14, H12
I
K13
J13
FEC0
FEC0_MDIO PFECI2C[5]
FEC0_MDC PFECI2C[4]
FEC0_TXCLK PFEC0H[7]
FEC0_TXEN PFEC0H[6]
FEC0_TXD[0] PFEC0H[5]
FEC0_COL PFEC0H[4]
FEC0_RXCLK PFEC0H[3]
FEC0_RXDV PFEC0H[2]
FEC0_RXD[0] PFEC0H[1]
FEC0_CRS PFEC0H[0]
FEC0_TXD[3:1] PFEC0L[7:5]
FEC0_TXER PFEC0L[4]
FEC0_RXD[3:1] PFEC0L[3:1]
FEC0_RXER PFEC0L[0]
I2C_SDA
I2C_SCL
—
—
—
—
—
—
—
—
—
—
—
—
U2RXD I/O
U2TXD O
—
I
—
O
—
O
—
I
—
I
—
I
—
I
—
I
—
O
—
O
—
I
—
I
A7
B7
C3
D4
G4
A6
B6
B5
C6
C7
E3, F3, F4
D3
D5, C5, D6
C4
A3
C5
C1
C3
D2
B4
B3
C4
D5
A2
D1, E3, D3
C2
D4, B1, B2
E4
FEC1
FEC1_MDIO PFECI2C[3]
—
—
I/O
G1
—
FEC1_MDC PFECI2C[2]
—
—
O
G2
—
FEC1_TXCLK PFEC1H[7]
—
—
I
C1
—
FEC1_TXEN PFEC1H[6]
—
—
O
D2
—
FEC1_TXD[0] PFEC1H[5]
—
—
O
F1
—
FEC1_COL PFEC1H[4]
—
—
I
A5
—
FEC1_RXCLK PFEC1H[3]
—
—
I
B4
—
FEC1_RXDV PFEC1H[2]
—
—
I
A3
—
FEC1_RXD[0] PFEC1H[1]
—
—
I
B3
—
FEC1_CRS PFEC1H[0]
—
—
I
A4
—
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor