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MCF5275LCVM133

Integrated Microprocessor Family Hardware Specification

Freescale Semiconductor 

1 SD VDD is nominally 2.5V.

Preliminary Electrical Characteristics

SDCLK

SDCLK

Figure 11. DDR Clock Timing Diagram

VIX

VMP VID

VIX

When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly

latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.

Table 15. DDR Timing

NUM

Characteristic1

Symbol

Min

Max

Unit

Frequency of operation2

TBD

83

MHz

DD1

DD2

DD3

DD4

Clock Period (DDR_CLKOUT)

Pulse Width High3

Pulse Width Low3

DDR_CLKOUT high to DDR address, SD_CKE,

SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid

tCK

tCKH

tCKl

tCMV

12

0.45

0.45

—

TBD

ns

0.55

tCK

0.55

tCK

0.5 x tCK + 1 ns

DD5 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,

tCMH

2

SD_SCAS, SD_SRAS, SD_WE invalid

—

ns

DD6

DD7

DD8

DD9

DD10

Write command to first SD_DQS Latching Transition

SD_DQS high to Data and DM valid (write) - setup4,5

SD_DQS high to Data and DM invalid (write) - hold4

SD_DQS high to Data valid (read) - setup6

SD_DQS high to Data invalid (read) - hold7

tDQSS

—

1.25

tCK

tQS

1.5

—

ns

tQH

1

—

ns

tIS

—

1

ns

tIH

0.25 x tCK + 1

—

ns

DD11 SD_DQS falling edge to CLKOUT high - setup

tDSS

0.5

—

ns

DD12 SD_DQS falling edge to CLKOUT high - hold

tDSH

0.5

—

ns

DD13 DQS input read preamble width (tRPRE)

tRPRE

0.9

1.1

tCK

DD14 DQS input read postamble width (tRPST)

tRPST

0.4

0.6

tCK

DD15 DQS output write preamble width (tWPRE)

tWPRE

0.25

—

tCK

DD16 DQS output write postamble width (tWPST)

tWPST

0.4

0.6

tCK

1 All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.

2 DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.

3 tCKH + tCKL must be less than or equal to tCK.

4 D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.

5 The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The

remaining data beats will be valid for each subsequent SD_DQS edge

6 Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data

line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or

other factors).

7 Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data

line becomes invalid.

Figure 13 shows a DDR SDRAM write cycle.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

29

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