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9S12E128DGV1

MC9S12E-Family Device User Guide V01.04

Motorola => Freescale 

Freescale SemiconDdevuiccetUoserr,GIunidce.— 9S12E128DGV1/D V01.04

List of Figures

Figure 0-1 Order Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 1-1 MC9S12E-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 1-2 MC9S12E256 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 23

Figure 1-3 MC9S12E128 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 24

Figure 1-4 MC9S12E64 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 1-5 MC9S12E32 User configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 2-1 Pin assignments 112 LQFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 76

Figure 2-2 Pin assignments in 80 QFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 77

Figure 2-3 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 2-4 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 20-1 Recommended PCB Layout (112 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 20-2 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . 118

Figure B-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure B-3 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure B-4 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure B-5 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure B-6 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure B-7 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure B-8 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure C-1 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 153

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