PACDN006S/T Ver la hoja de datos (PDF) - California Micro Devices => Onsemi
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PACDN006S/T Datasheet PDF : 6 Pages
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CALIFORNIA MICRO DEVICES
PAC DN006
Input Capacitance vs. Input Voltage
5
4
3
2
1
0
0
1
2
3
4
5
Input Voltage
Typical variation of CIN with VIN. (VP=5V, VN=0V)
STANDARD PART ORDERING INFORMATION
Package
Ordering Part Number
Pins
Style
Tubes
Tape & Reel
8
SOIC
PACDN006S/T
PACDN006S/R
8
MSOP
PACDN006M/T
PACDN006M/R
Part Marking
PDN006S
D006
Application Information
See also California Micro Devices Application Note AP 209, Design Considerations for ESD Protection.
In order to realize the maximum protection against ESD pulses with the PAC DN006, care must be taken in the PCB layout
to minimize the parasitic series inductance to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of
a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the
power supply is represented by L1. The voltage VZ on the line being protected is:
VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply
where Iesd is the ESD current pulse, and VSupply is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, consider the case of an ESD
pulse that rises from zero to 10 Amps in 1nS. Here d(Iesd)/dt can be approximated by ∆Iesd/∆t, or 10/(1x10-9). So each
nano Henry of series inductance (L1) will lead to a 10V increment in VZ.
©1999 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
Rev 1 3/99
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