56F8156 Ver la hoja de datos (PDF) - Freescale Semiconductor
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56F8156 Datasheet PDF : 178 Pages
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)
Signal Name Pin No. Type
State
During
Reset
Signal Description
A0
138
Output
In reset, Address Bus — A0 - A5 specify six of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled register (BCR), A0 - A5 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA8)
A1
(GPIOA9)
Input/
Output
10
A2
11
(GPIOA10)
A3
12
(GPIOA11)
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A4
13
(GPIOA12)
A5
14
(GPIOA13)
A6
17
Output
In reset, Address Bus — A6 - A7 specify two of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled register (BCR), A6 - A7 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOE2)
A7
(GPIOE3)
Schmitt
Input/
18
Output
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
56F8356 Technical Data, Rev. 13
20
Freescale Semiconductor
Preliminary
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