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56F8156 Ver la hoja de datos (PDF) - Freescale Semiconductor

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componentes Descripción
Fabricante
56F8156
Freescale
Freescale Semiconductor Freescale
56F8156 Datasheet PDF : 178 Pages
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2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
VDD_IO
1
VDD_IO
16
VDD_IO
31
VDD_IO
38
VDD_IO
66
VDD_IO
84
VDD_IO
119
VDDA_ADC
102
VDDA_OSC_PLL
80
Supply
Supply
Supply
VSS
VSS
VSS
VSS
VSS
VSSA_ADC
27
Supply
37
63
69
144
103
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage
regulator, if it is enabled.
ADC Power — This pin supplies 3.3V power to the ADC modules.
It must be connected to a clean analog power supply.
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.
VSS — These pins provide ground for chip logic and I/O drivers.
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
56F8356 Technical Data, Rev. 13
18
Freescale Semiconductor
Preliminary

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