Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC/PLL)
(ROSC)
Timer A
4
Quadrature Decoder 0
2
FlexCAN
4
2
SCI 1
SPI 0
GPIO A
GPIO B
GPIO C
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
SIM
RESET
COP Reset
COP
SPI 1
PWMA
SCI 0
4
3
SYNC Output
2
ch2i
2
Timer C
ch2o
ADCA
6
TEMP_SENSE
Not available on the 56F8122 device.
IPBus
The dotted line on Temperature Sense signifies the
pad-to-pad bond between TEMP_SENSE and
ANA7 on the 56F8322
Figure 1-2 Peripheral Subsystem
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
11
Preliminary