MC33989D Ver la hoja de datos (PDF) - Motorola => Freescale
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MC33989D Datasheet PDF : 23 Pages
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MC33989
(Vsup From 5.5V to 18V and Tj from -40°C to 150°C)
For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section
Description
Temperature Threshold difference
Reset threshold 1
Symbol
Tsd-Tpw
Rst-th1
Characteristics
Min
Typ
Max
20
40
4.3
4.5 V
4.7
Reset threshold 2
Reset duration
Vdd1 range for Reset Active
Reset Delay Time
Line Regulation
Line Regulation
Load Regulation
Thermal stability
Rst-th2
3.6
3.8
4
reset-dur
1
2
Vddr
1
td
5
LR1
20
5
25
LR2
10
25
LD
20
50
ThermS
5
Unit
°C
ms
V
µs
mV
mV
mV
mV
Conditions
Selectable by SPI. Default
value after reset.
Selectable by SPI
9V<Vsup<18, Idd=10mA
5.5V<Vsup<27V, Idd=10mA
1mA<IIdd<200mA
Vsup=13.5V, I=100mA
V2 adjustable output voltage regulator
Note 3: V2 specification with external capacitor
- option 1: C>22uF and ESR<1O ohm, (no tantalum capacitor required)
- option2: C>1uF and ESR<10 ohm, (no tantalum capacitor required). In this case depending upon ballast transistor gain an additional resistor
and capacitor network between emitter and base of PNP ballast transistor might be required (ex C=10nF).
Note 4: Subject to external R1 and R2 resistors tolerances.
V2 Output Voltage (note 4)
V2
4,9
5
5,1
V
I2 from 2 to 200mA
5.5V< Vsup <27V
I2 output current (for information only)
I2
200
mA
Depending upon external
ballast transistor
V2 sense reference voltage
V2sref
1.25
V
V2 ctrl drive current
I2ctrl
10
mA
V2 ctrl Output voltage range
V2ctrl
1.8
8
V
(Vsup>V2ctrl+1V)
Vdd2 to Vdd1 matching (note 4)
Vmatch
0.5
0.5
%
excluding external compo-
nent matching
Logic output pins (MISO)
Low Level Output Voltage
Vol
1.0
V
I out = 1.5mA
High Level Output Voltage
Voh
Vdd1-0.9
V
I out = -250uA
Tristated MISO Leakage Current
-2
+2
µA
0V<Vmiso<Vdd
Logic input pins (MOSI, SCLK, CSB)
High Level Input Voltage
Vih
0.7Vdd1
Vdd1+0.3
Low Level Input Voltage
Vil
-0.3
0.3Vdd1
V
High Level Input Current on CSB
Low Level Input Current CSB
MOSI, SCK Input Current
Reset Pin (output pin only)
Iih
-20
Iil
-20
Iin
-10
-100
µA
-100
µA
10
µA
Vi=4V
Vi=1V
0<VIN<Vdd
High Level Output current
Low Level Output Voltage (I0=1.5mA)
Reset pull down current
Iol
Vol
0
Ipdw
3
-30
µA
0.9
V
5
mA
0<Vout<0.7Vdd
1v<Vsup<27V
Reset Duration after Vdd1 High
reset-dur
1
2
ms
Wdogb output pin
Low Level Output Voltage (I0=1.5mA)
High Level Output Voltage (I0=-250uA)
INT Pin
Vol
0
Voh
Vdd1-0.9
0.9
V
1v<Vsup<27V
Low Level Output Voltage (I0=1.5mA)
High Level Output Voltage (I0=-250uA)
HS1: 150mA High side output pin
Vol
0
Voh
Vdd1-0.9
0.9
V
4
System Basis Chip With High Speed CAN Transceiver
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