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MC33989D

System Basis Chip With High Speed CAN Transceiver

Motorola => Freescale 

MC33989

In stop mode the Software watchdog can be “running” or “not running” depending upon selection by SPI. Refer to table 1 and

SPI description.

In stop mode, SBC wake up capability are identical as in sleep mode. refer to table 1.

4.5.4.1 Application wake up from SBC side:

When application is in stop mode, it can wake up from the SBC side. When a wake up is detected by the SBC (ex CAN, Wake

up input etc.) the SBC turns itself into Normal request mode. The wake up is signalled to the MCU through the INT pin. INT pin is

pulled low for 10us and then returns high. Wake up event can be read through the SPI registers.

4.5.4.2 Application wake up from MCU side:

When application is in stop mode, the wake up event may come to the MCU. In this case the MCU has to signal to the SBC

that it has to go into Normal mod in order for the Vdd1 regulator to be able to deliver full current capability. This is done by a low

to high transisiton of the CSB pin. CSB pin low to high activation has to be done as soon as possible after the MCU.

Alternatively the L0 , L1, L2 and L3 inputs can also be used as wake up from stop mode.

4.5.4.3 Software watchdog in stop mode:

If watchdog is enabled, the MCU has to wake up independently of the SBC before the end of the SBC watchdog time. In

order to do this the MCU has to signals the wake to the SBC through the SPI wake up (CSB activation). Then the SBC wakes up

and jump into the normal request mode. MCU has to configured the SBC to go to either normal or standby mode. The MCU can

then decide to go back again to stop mode.

If no MCU wakes up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request

mode. The MCU can then be initialized.

4.5.5 Normal request mode:

This is a temporary mode automatically accessed by the device after a wake up event from sleep or stop mode or after

device power up. In this mode the Vdd1 regulator is ON, V2 is off, the reset pin is high. As soon as the device enters the normal

request mode an internal 400ms timer is started. During these 400ms the micro controller of the application must addressed the

SBC via SPI and configure the watchdog register. This is the condition for the SBC to stop the 400ms timer and to go into the

Normal mode and to set the watchdog timer according to configuration.

If no SPI configuration occurs within the 400ms, two cases must be considered:

- The “BATFAIL flag” has not been cleared: in this case the SBC goes to reset mode for 1ms, then return to normal request

mode. If no W/D configuration is done within 400ms, the SBC goes to reset again, then normal request etc.

- If the “BATFAIL flag” has been reset, the SBC will goes back to previous low power mode. For instance If SBC was in sleep

mode prior to the wake up it returns to sleep mode and keep the same wake up event configuration.

If SBC was in stop mode, it return to stop mode and keep the same wake up event configuration.

After an SBC power up (Vsup rising from zero to nominal), and if BATFAIL flag is cleared (MCR register read) the default low

power mode is sleep mode.

“BATFAIL flag” is a bit which is triggered when Vsup is below 3V. This bit is set into the MCR register. It is reset by MCR

register read.

4.5.6 Reset and watchdog: mode1 and mode 2 (safe mode):

The watchdog and reset functions have two modes of operation: mode 1 and mode 2 (mode 2 is also called safe mode).

These modes are independent of the SBC modes (Normal, stand-by, sleep, stop). Mode 1 or mode 2 selection is done through

SPI (register MCR, bit SAFE). Default mode after reset is mode 1.

4.6

Internal Clock

The device has an internal clock used to generate all timings (reset, watchdog, cyclic wake up, filtering time etc....).

4.7

Reset pin

A reset output is available in order to reset the microcontroller. Two operation modes for the reset pin are available, mode 1

and mode 2 (refer to table for reset pin operation).

The reset cause when SBC is in mode 1 are:

- Vdd1 falling out of range: if Vdd1 falls below the reset threshold (parameter Rst-th), the reset pin is pull low until Vdd1 return

to nominal voltage.

- Power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until Vdd1 is within

its operation range.

- Watchdog time out: if the watchdog is not cleared the SBC will pull the reset pin low for the duration of the reset duration

time (parameter: reset-dur).

In mode 2, the reset pin is not activated in case of watchdog time out. Refer to” table for reset pin operation“for mode detail.

For debug purposes at 25°C, reset pin can be shorted to 5V.

4.8

Software watchdog (selectable window or time out watchdog)

Software watchdog is used in the SBC normal and stand-by modes for the MCU monitoring. The watchdog can be either

window or time out. This is selectable by SPI (register TIM1, bit WDW). Default is window watchdog. The period for the

watchdog is selectable from SPI from 5 to 400ms (register TIM1, bits WDT0 and WDT1). When the window watchdog is

selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The

System Basis Chip With High Speed CAN Transceiver

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