MC33886 Ver la hoja de datos (PDF) - Motorola => Freescale

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Fabricante

MC33886

5.0 A H BRIDGE

Motorola => Freescale 

Freescale Semiconductor, Inc.

DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

PWM Frequency (Note 20)

f PWM

–

–

10

kHz

Maximum Switching Frequency During Active Current Limiting (Note 21)

f MAX

–

–

20

kHz

Output ON Delay (Note 22)

V+ = 14 V

t d (ON)

–

µs

–

18

Output OFF Delay (Note 22)

V+ = 14 V

t d(OFF)

–

µs

–

18

Output Rise and Fall Time (Note 23)

V+ = 14 V, IOUT = 3.0 A

tf, tr

µs

2.0

5.0

8.0

Output Latch-OFF Time

ta

15

20.5

26

µs

Output Blanking Time

tb

12

16.5

21

µs

Output FET Body Diode Reverse Recovery Time (Note 24)

trr

100

–

–

ns

Disable Delay Time (Note 25)

t d(disable)

–

–

8.0

µs

Short Circuit/Overtemperature Turn-OFF Time (Note 26)

t FAULT

–

4.0

–

µs

Power-OFF Delay Time

t pod

–

1.0

5.0

ms

Notes

20. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse

train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer

to Typical Switching Waveforms, Figures 11 through 18, pp. 12–13.

21. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-

time PWM of the output. The output load current effects the Maximum Switching Frequency.

22. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition

direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90%

point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10%

point of the output response signal. See Figure 2, page 8.

23. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 8.

24. Parameter is guaranteed by design but not production tested.

25. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3,

page 8.

26. Increasing currents will become limited at ILIM. Hard shorts will breach the ISCH or ISCL limit, forcing the output into an immediate tri-state

latch-OFF. See Figures 6 and 7, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature above 160°C

will cause the active current limiting to progressively "fold back" (or decrease) to 2.5 A typical at 175°C where thermal latch-OFF will occur.

See Figure 5, page 8.

MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDEoVrIeCEIDnAfoTArmation On This Product,

Go to: www.freescale.com

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