MC33298DW Ver la hoja de datos (PDF) - Freescale Semiconductor

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componentes Descripción

Fabricante

MC33298DW

Eight Output Switch with Serial Peripheral Interface I/O

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

SCLK

tR (SI)

< 10 ns

0.7VDD

50%

tDLY(LH)

SO

(Low-to-High)

SO

(High-to-Low)

0.2VDD

tVALID

0.7VDD

tR (SO)

tF (SO)

tDLY(HL)

tF (SI)

< 10ns

5.0V

0.7VDD

0.2VDD 0

V0H

V0L

V0H

0.2 VDD

V0L

SO (Low-to-High) is for an output with internal conditions such that

the low-to-high transition of CS causes the SO output to switch from

high to low.

Figure 7. Valid Data Delay Time and

Valid Time Waveforms

CS

0.2VDD

SO

(High-to-Low)

SO

(Low-to-High)

tR(S<I) 10 ns

90%

10%

tSO(EN)

90%

tSO(EN)

10%

tF(S<I) 10 ns

0.7 VDD

5.0 V

0

tSO(DIS)

VTri-State

10%

tSO(DIS)

90%

tSO(dis)

V0H

VTri-State

1. SO (high-to-low) waveform is for SO output with internal conditions such

that SO output is low except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state, e.g. open load.

2. SO (low-to-high) waveform is for SO output with internal conditions such

that SO output is high except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state, e.g. shortened load.

Figure 8. Enable and Disable Time Waveforms

VDD = 5.0V

VPWR = 14V

33298

CS

Under

Test

RL = 26Ω

Output

CL

CL represents the total capacitance of the test fixture and probe.

Figure 9. Switching Time Test Circuit

VDD = 5.0V

VPWR = 11V

33298

CS

Under

Test

IL = 2.0A

(Output ΟΝ)

Output

CL = 20 pF

CL represents the total capacitance of the test fixture and probe.

Figure 10. Output Fault Unlatch Disable

Delay Test Circuit

Analog Integrated Circuit Device Data

Freescale Semiconductor

33298

11

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