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MC145181 Datasheet PDF : 71 Pages
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Freescale SMeCm14i5c1o8n1 ductor, Inc.
3E. DAC CHARACTERISTICS
Vpos = 1.8 to 3.6 V, DAC Vpos = 1.8 to 3.6 V; TA = –40 to 85°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parameter
Condition
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Resolution
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Integral Nonlinearity
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Offset Voltage from Gnd
No External Load
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Offset Voltage from DAC Vpos
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Output Impedance
No External Load
Over Entire Output Range, Including Zero
Output (which is Low–power Standby)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Standby Current
Zero Output, No External Load
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Supply Current per DAC @ DAC Vpos pin Except with Zero Output, No External Load
Guaranteed
Limit
Unit
8
Bits
±1
LSB
1
LSB
2
LSB
130
k
(See ISTBY in Section 3B)
(DAC Vpos) / 36
mA
3F. VOLTAGE MULTIPLIER AND KEEP–ALIVE OSCILLATOR CHARACTERISTICS
Voltages Referenced to Gnd, TA = –40 to 85°C
Guaranteed
Parameter
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage Multiplier Output Voltage
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Keep–alive Refresh Frequency
Condition
5 MHz Refresh Rate, 100 µA Continuous
Sourcing, Measured at Cmult pin
Vpos = 1.8 V
Vpos = 3.6 V
Vpos = 1.8 to 3.6 V
Limit
Unit
3.32 to 3.78
V
4.75 to 5.35
300 to 700
kHz
3G. DYNAMIC CHARACTERISTICS OF DIGITAL PINS
Vpos = 1.8 to 3.6 V, TA = –40 to 85°C, Input tr = tf = 10 ns, CL = 25 pF
Parameter
Figure
No.
Symbol
Guaranteed
Limit
Unit
Serial Data Clk Frequency
NOTE: Refer to Clk tw Below
1
fclk
dc to 10
MHz
Maximum Propagation Delay, Enb to Output A (Selected as General–Purpose Output)
2, 7
tPLH, tPHL
200
ns
Maximum Propagation Delay, Enb to Output B
2, 3, 7, 8 tPLH, tPHL,
200
ns
tPZL, tPLZ,
tPZH, tPHZ
Maximum Propagation Delay, Enb to Output C
4, 8
tPZL, tPLZ
200
ns
Maximum Output Transition Time, Output A; Output B with Active Pullup and Pulldown
2, 7
tTLH, tTHL
75
ns
Minimum Setup and Hold Times, Din versus Clk
5
tsu, th
30
ns
Minimum Setup, Hold, and Recovery Times, Enb versus Clk
6
tsu, th, trec
100
ns
Minimum Pulse Width, Inactive (High) Time, Enb
6
tw
*
cycles
Minimum Pulse Width, Clk
1
tw
50
ns
Maximum Input Capacitance — Din, CLK, Enb
Cin
10
pF
* For Hr register access, the minimum limit is 20 Osce cycles.
For Hni register access, the minimum limit is 27 fini cycles.
For N register access, the minimum limit is 20 Osce cycles + 99 fin cycles.
When the timer is used for adapt, the minimum limit after the second N register access and before the next register access is the time–out interval + 99 fin cycles.
6
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com

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