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MC145181

Dual 550/60 MHz PLL Frequency Synthesizer with DACs and Voltage Multiplier

Motorola => Freescale

MC145181 Datasheet PDF : 71 Pages

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Freescale SMeCm14i5c1o8n1 ductor, Inc.

5. PIN DESCRIPTIONS

5A. DIGITAL PINS

Data is retained in the registers over a supply range of 1.8

to 3.6 V. The bit–stream formats are shown in Figures 13

through 18.

Enb, Din, and Clk

Pins 5, 6, and 7 — Serial Data Port Inputs

The Enb input is used to activate the serial interface to

allow the transfer of data to the device. To transfer data to the

device, the Enb pin must be low during the interval that the

data is being clocked in. When Enb is taken back high

(inactive), data is transferred to the appropriate register

depending either on the data stream length or address bits.

The C, Hr, and N registers can be accessed using either a

unique data stream length (BitGrabber) or by using address

bits (Conventional). The D, Hni, and Ri registers can only be

accessed using address bits. See Table 1.

The bit stream begins with the MSB and is shifted in on the

low–to–high transition of Clk. The bit pattern is 1 byte (8 bits)

long to access the C register, 2 bytes (16 bits) to access the

Hr register, or 3 bytes (24 bits) to access the N register. A bit

pattern of 4 bytes (32 bits) is used to access the registers

when using address bits. The device has double buffers for

storage of the Ni and R counter divide ratios. One double

buffer is composed of the Hr register which feeds the R

which feeds the Ni register. An Hni to Ni register transfer

occurs whenever the N register is written. Thus, new divide

ratios may be presented to the R, Ni, and N counters

simultaneously.

Transitions on Enb must not be attempted while Clk is

high. This puts the device out of synchronization with the

microcontroller. Resynchronization occurs whenever Enb is

high (inactive) and Clk is low.

Pin 8 — Lock Detectors Output

This signal is the logical AND of the lock detect signals

from both PLL and PLLi. For the main PLL, the phase

window that defines “lock” is programmable via bit N22. The

phase window for the secondary PLLi is not programmable.

If either PLL or PLLi is in standby, LD indicates the lock

condition of the active loop only. If both loops are in standby,

the LD output is a static low level.

Each PLL’s lock detector is in the high state when the

respective loop is locked (the inputs to the phase detector

being the same phase and frequency). The lock detect signal

is in the low state when a loop is out of lock. See Figure 19.

Upon power up, the LD pin indicates a not locked

condition. The LD pin is a push–pull CMOS output. If unused,

LD should be left open.

Output A

Pin 9 — Multiple–Purpose Digital Output

Depending on control bits Ri21 and Ri20, Output A is

selectable by the user as a general–purpose output (either

high or low level), fR (output of main reference counter), fRi

(output of secondary reference counter), or a phase detector

pulse indicator for both loops. When selected as

general–purpose output, bit C7 determines whether the

output is a high or low level per Table 2. When configured as

fR, fRi, or phase detector pulse, Output A appears as a

normally low signal and pulses high.

Output A is a slew–rate limited CMOS totem–pole output.

If unused, Output A should be left open.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Access

Type

Table 1. Register Access

(LSBs are C0, R0, N0, D0, Ri0, and Ni0)

Accessed Address

Number

Clocks

Nomenclature

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BitGrabber

—

C7, C6, C5, ..., C0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BitGrabber

—

R15, R14, R13, ..., R0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BitGrabber

—

N23, N22, N21, ..., N0