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MC14513BCP
(Rev.:2000)

BCD-To-Seven Segment Latch/Decoder/Driver

ON Semiconductor 

MC14513B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

– 55_C

25_C

125_C

Characteristic

Symbol Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max Unit

Output Drive Current — RBO Output IOH

(VOH = 2.5 V)

Source

(VOH = 9.5 V)

(VOH = 13.5 V)

5.0 – 0.40

—

– 0.32 – 0.64

10 – 0.21

—

– 0.17 – 0.34

15 – 0.81

—

– 0.66 – 1.30

mAdc

—

– 0.22

—

—

– 0.12

—

—

– 0.46

—

(VOL = 0.4 V)

(VOL = 0.5 V)

(VOL = 1.5 V)

Sink IOL

5.0

0.18

—

0.15

0.29

10

0.47

—

0.38

0.75

15

1.80

—

1.50

2.90

—

0.10

— mAdc

—

0.26

—

—

1.0

—

Output Drive Current — Segments

IOL

(VOL = 0.4 V)

Sink

(VOL = 0.5 V)

(VOL = 1.5 V)

Input Current

Iin

5.0

0.64

—

0.51

0.88

10

1.6

—

1.3

2.25

15

4.2

—

3.4

8.8

mAdc

—

0.36

—

—

0.9

—

—

2.4

—

15

—

± 0.1

— ± 0.00001 ± 0.1

—

± 1.0 µAdc

Input Capacitance

Quiescent Current

(Per Package) Vin = 0 or VDD,

Iout = 0 µA

Total Supply Current (5.) (6.)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

Cin

—

—

—

—

5.0

7.5

—

—

pF

IDD

5.0

—

5.0

—

0.005

5.0

—

150 µAdc

10

—

10

—

0.010

10

—

300

15

—

20

—

0.015

20

—

600

IT

5.0

10

15

IT = (1.9 µA/kHz) f + IDD

IT = (3.8 µA/kHz) f + IDD

IT = (5.7 µA/kHz) f + IDD

µAdc

4. Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level =

1.0 Vdc min @ VDD = 5.0 Vdc

2.0 Vdc min @ VDD = 10 Vdc

2.5 Vdc min @ VDD = 15 Vdc

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.

All outputs connected to respective CL loads.

20 ns

A, B, AND C

20 ns

90%

VDD

50%

1

10%

VSS

2f

50% DUTY CYCLE

VOH

ANY OUTPUT

50%

VOL

Figure 1. Dynamic Power Dissipation Signal Waveforms

http://onsemi.com

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