MC14076BDR2G(2014) Ver la hoja de datos (PDF) - ON Semiconductor

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MC14076BDR2G
(Rev.:2014)

4-Bit D-Type Register with Three-State Outputs

ON Semiconductor 

MC14076B

4-Bit D-Type Register

with Three-State Outputs

The MC14076B 4−Bit Register consists of four D−type flip−flops

operating synchronously from a common clock. OR gated

output−disable inputs force the outputs into a high−impedance state

for use in bus organized systems. OR gated data−disable inputs cause

the Q outputs to be fed back to the D inputs of the flip−flops. Thus they

are inhibited from changing state while the clocking process remains

undisturbed. An asynchronous master root is provided to clear all four

flip−flops simultaneously independent of the clock or disable inputs.

Features

• Three−State Outputs with Gated Control Lines

• Fully Independent Clock Allows Unrestricted Operation for the

Two Modes: Parallel Load and Do Nothing

• Asynchronous Master Reset

• Four Bus Buffer Registers

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

http://onsemi.com

SOIC−16

D SUFFIX

CASE 751B

MARKING DIAGRAM

16

14076BG

AWLYWW

1

A

WL, L

YY, Y

WW, W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

Vin, Vout

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

−0.5 to +18.0

V

−0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

±10

mA

PD

Power Dissipation, per Package (Note 1)

TA

Ambient Temperature Range

Tstg

Storage Temperature Range

TL

Lead Temperature

(8−Second Soldering)

500

mW

−55 to +125

°C

−65 to +150

°C

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be

taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout

should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2014

1

August, 2014 − Rev. 8

Publication Order Number:

MC14076B/D

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