MC13077 Ver la hoja de datos (PDF) - Motorola => Freescale
Número de pieza
componentes Descripción
Fabricante
MC13077 Datasheet PDF : 14 Pages
| |||
MC13077
4x fsc
Crystal
5–25 pF
Figure 4. Versatility of the 4x fsc Oscillator
8
MC13077
9
Oscillator Free
Run with Crystal
4x fsc Drive
(150 mV to 3.0 Vpp)
220
1000 pF
8
150 p
9
MC13077
Direct Drive of
Oscillator with
4x fsc Source
4x fsc
Crystal
8
5–25 pF 1000 pF
fsc
9
Subcarrier Reference
Input (Pull–in Range
of ± 400 Hz)
MC13077
Oscillator Phase Lock
with Crystal to
Subcarrier Reference
Subcarrier
Reference Input
4x fsc
Resonator
8
1000 pF
9
MC13077
Oscillator Phase Lock
with Resonator to
Subcarrier Reference
4X Subcarrier Oscillator
To encode the color difference components, an accurate
and reliable subcarrier source is required. The MC13077 has
an on–chip single pin oscillator that will free–run with a 4x fsc
crystal, phase–lock to an external subcarrier reference with a
4x fsc crystal or resonator, or be driven externally from a 4x fsc
source. If the 4x fsc oscillator is going to be free run, the
subcarrier input (Pin 9) should be grounded. If the 4x fsc
oscillator is going to be phase–locked to an external
subcarrier source, the external reference should be
capacitor–coupled to Pin 9. If the 4x fsc oscillator is going to
be driven externally, Pin 8 should be driven from a network
that increases the impedance of the source at frequencies
capable of producing off–frequency oscillations. The 4x fsc
subcarrier source, thus being defined, makes it possible to
produce accurate quadrature subcarriers for the modulators.
The 4x source is internally divided by a ring counter to
produce the quadrature subcarrier signals. These signals in
turn are provided to the color difference modulators to
produce the modulated chroma. The oscillator was designed
so that if a crystal is chosen as the resonant element of the 4x
oscillator, the crystal specifications would be common.
Crystal specifications for an adequate crystal are shown in 1
Table 1. Crystal Specifications
Frequency: 14.31818 MHz (NTSC)
17.734475 MHz (PAL)
Mode: Fundamental
Frequency Tolerance (@25°C), 40 ppm
Frequency Tolerance df/dfo (0° – 70°C), 40 ppm
Load Capacitance: 20 pF
ESR: 50 Ω
C1(Internal Series Capacitance), 15 mpF
This crystal is a common variety and is specified as a parallel resonant.
Burst Flag Decoding
In order to encode to either NTSC or PAL compatibility, the
MC13077 must first determine which is the intended
standard. The MC13077 accomplishes this with an internal
decode using the sync input and the output of the divide by 4
ring counter. Internally, the Sync separator circuitry provides
an output that is sampled by the subcarrier signal from the
MOTOROLA ANALOG IC DEVICE DATA
ring counter. The result is an internal sync representative of
externally input sync but synchronized to the internal
subcarrier signal. This signal provides a reset for an internal
9–bit counter that provides divisions of the subcarrier signal
from the ring counter at powers of 2 (i.e. 21, 22, 23,...29 =
512). The eighth bit of the counter gives the output, fsc ÷ 256.
The decision to provide burst gate timing for PAL or NTSC is
based upon the state of this output after one period of the
horizontal sync. Figure 5 shows the relationship between the
clock and the eighth bit of the counter.
Triggering of the burst PAL flip–flop due to equalizing
pulses is also inhibited by the decode circuitry. This is done
by counting out beyond a half line interval before generating
burst flag.
If the MC13077 is encoding 525/60 component video to
NTSC and the MC13077 is generating the burst flag, the start
of burst will occur 18 counts after the leading edge of sync
has been sampled, and will continue until nine cycles of burst
have occurred. Since the reset pulse of the 9–bit counter has
a resolution of 1.0/fsc, this implies that the start of burst will
occur 5.17 ± 0.1397 µs after the leading edge of sync and
also that the start (and end) of burst may differ by as much as
279.4 ns from line–to–line. If the MC13077 is encoding
625/50 to PAL, the subcarrier frequency will be
4.43361875 MHz and that implies a resolution of 225.5 ns
for the burst position. For PAL encoding, 24 counts of the
subcarrier are necessary before burst is initiated. So ten
cycles of subcarrier will occur 5.53 ± 0.1128 µs after the
leading edge of sync. After the timing of the burst gate is
selected, the burst gate envelope is added to the color
difference components.
Another alternative to the internal determination of burst
flag is the external input of burst flag. This allows the user to
externally define the exact timing and duration of color burst.
If external burst flag is available, it can be inserted at Pin 18.
The threshold level is nominally VCC/2 and the input should
not exceed VCC. Burst will begin when the leading edge of
the burst flag input exceeds VCC/2 and will stop when it falls
below VCC/2. If it is desired to disable the burst flag, Pin 18
can be pulled low. It is also possible to insert burst flag with
the R–Y and B–Y components. This is done at the clamp pins
with the respective color difference inputs with the internal
burst flag generation disabled (Pin 18 grounded).
7
Share Link: 