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MC100EP56 Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza
componentes Descripción
Fabricante
MC100EP56 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
MC10EP56, MC100EP56
Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
fmax
tPLH,
tPHL
Maximum Frequency
(See Figure 2 Fmax/JITTER)
>3
>3
>3
GHz
Propagation Delay to
ps
Output Differential
D to Q, Q 250 340 450 270 360 470 300 400 500
SEL to Q, Q 250 340 450 270 340 470 300 400 500
COM_SEL to Q, Q 250 350 450 270 360 470 300 400 500
tSKEW
WithinDevice Skew (Note 21)
Device to Device Skew
50 100
200
50 100
200
50 100 ps
200
tJITTER
VPP
Random Clock Jitter
(See Figure 2 Fmax/JITTER)
Input Voltage Swing
(Differential Configuration)
0.2 < 1
0.2 < 1
0.2 < 1 ps
150 800 1200 150 800 1200 150 800 1200 mV
tr
Output Rise/Fall Times
Q, Q 70 120 170 80 130 180 100 150 230 ps
tf
(20% 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
1000
10
9
5V
8
800
7
3.3 V
6
600
5
4
3
ÉÉ 400
2
ÉÉ (JITTER)
1
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 200
0
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 2. Fmax/Jitter @ 255C
Q
Driver
Device
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
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