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MC100EP31 Datasheet PDF : 11 Pages
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MC10EP31, MC100EP31
3.3V / 5V ECL D Flip−Flop
with Set and Reset
Description
The MC10/100EP31 is a D flip−flop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip−flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
Features
The 100 Series contains temperature compensation.
• 340 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at VEE
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
HEP31
ALYW
G
1
8
KEP31
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP31
ALYWG
G
1
8
KP31
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10
A = Assembly Location
K = MC100
L = Wafer Lot
5O = MC10
Y = Year
3J = MC100
W = Work Week
M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 9
Publication Order Number:
MC10EP31/D
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