MC100LVEL37DWG(2016) Ver la hoja de datos (PDF) - ON Semiconductor

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componentes Descripción

Fabricante

MC100LVEL37DWG
(Rev.:2016)

3.3 V ECL 1:4 ÷1/÷2 Clock Fanout Buffer

ON Semiconductor 

MC100LVEL37

Q

Driver

Device

Q

Zo = 50 W

Zo = 50 W

50 W

50 W

D

Receiver

Device

D

VTT

VTT = VCC − 2.0 V

Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices)

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D − ECLinPSt I/O SPiCE Modeling Kit

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

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