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MC100EPT21DR2 Ver la hoja de datos (PDF) - ON Semiconductor

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MC100EPT21DR2 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MC100EPT21
NC 1
D2
8 VCC
LVTTL
7Q
D3
LVPECL
VBB 4
6 NC
5 GND
Figure 1. Logic Diagram and 8−Lead Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
Q
D**, D**
VCC
VBB
GND
NC
FUNCTION
LVTTL/LVCMOS Output
Differential LVPECL/LVDS/CML Input
Positive Supply
Output Reference Voltage
Ground
No Connect
EP
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
** Pins will default to VCC/2 when left open.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
50 kW
50 kW
> 1.5 kV
> 100 V
> 2 kV
Level 1
UL 94 V−0 @ 0.125 in
81 Devices
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Power Supply
GND = 0 V
VIN
PECL Input Voltage
GND = 0 V
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
VI  VCC
SO−8
SO−8
3.8
0 to 3.8
± 0.5
−40 to +85
−65 to +150
190
130
V
V
mA
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case) Standard Board
SO−8
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
41 to 44
185
140
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case) Standard Board
TSSOP−8
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44
129
84
°C/W
°C/W
°C/W
Tsol
Wave Solder
Pb < 2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
°C
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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