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MB91F346B

32-bit Microcontroller

Fujitsu 

MB91345 Series

• On-chip multiplier supported at instruction level

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

• Harvard architecture allowing program access and data access to be executed simultaneously

• Instruction set compatible with FR family

• External bus interface

• Operating frequency : Max 25 MHz

• 24-bit address full output (16 Mbytes area)

• 8/16-bit data output

• Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum

• Support for various memory interfaces : SRAM and ROM/Flash

• Basic bus cycle : 2 cycles

• Programmable automatic wait cycle generator capable of inserting wait cycles for each area

• External wait cycles generated by RDY input

• Unused data/address pins can serve for general-purpose I/O

• Internal memory

MB91F345B

MB91F346B

Flash

512 Kbytes

1 Mbyte

D-bus RAM

24 Kbytes

24 Kbytes

F-bus RAM

8 Kbytes

8 Kbytes

• DMAC (DMA Controller)

• 5 channels

• Two transfer factors (internal peripheral / software)

• Addressing mode : 20/24-bit full-address selection (increment/decrement/fixed)

• Transfer modes (burst transfer/step transfer/and block transfer)

• Selectable transfer data sizes : 8, 16, or 32 bits

• Bit search module (for REALOS)

Search for the position of the bit I/O-changed first in one word from the MSB

• Reload timer : 3 channels (including 1channel for REALOS)

• 16-bit timer

• The internal clock is optional from 2/8/32 division

• Multi function serial interface

• 11 channels

• Full duplex double buffer

• 2 channels out of 11 channels with 16-byte FIFO

• Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication, clock

synchronous communication (Max 8.25 Mbps) , I2C* standard mode (Max 100 kbps) , high-speed mode (Max

400 kbps)

• Parity on/off selectable

• Baud rate generator per channel

• Abundant error detection functions are provided (Parity, frame, and overrun)

• External clock can be used as transfer clock

• ch.0, ch.1, ch.2, and ch.10 is tolerant of 5 V

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