MB89590B/BW Series
(Continued)
• PLL clock control
The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise character-
istics.
(6 MHz externally supplied clock : Internal system clock oscillated at 12 MHz)
• Various timers
8-bit PWM timer (can be used as either 8-bit PWM timer × 2 channels or PPG timer × 1 channel)
Internal 21-bit timebase timer
• Internal USB transceiver circuit (Compatible with high and low speeds)
• USB hub
Compliant to USB Protocol Revision 1.0
Five downstream port channels (One of these channels is dedicated to a function.)
Automatically responds to all USB protocols by hardware.
Descriptor configuration information is provided as ROM data for automatic responding by hardware (vendor
ID and product ID) .
* String data is not supported.
Allows switching between BUS power supply and own power supply modes.
Power supply to the USB down ports is controlled port by port.
• USB function
Compliant to USB Protocol Revision 1.0
Support for full speed
Allows four endpoints to be specified at maximum.
Types of transfer supported : control/interrupt/bulk/isochronous
Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for
function’s send and receive data.)
• UART/serial interface
Built-in UART/SIO function (selectable by switching)
• External interrupt
External interrupt (level detection × 8 channels)
Eight inputs are independent of one another and can also be used for resetting from low-power consumption
mode (the L-level detection feature available) .
• Low power consumption (standby mode supported)
Stop mode (There is almost no current consumption since oscillation stops.)
Sleep mode (This mode stops the running CPU.)
• A maximum of 45 general-purpose I/O ports
General-purpose I/O ports (CMOS) : 34
General-purpose output ports (CMOS) : 8
General-purpose I/O ports (Nch open drain) : 3
• Power supply
Supply voltage : 3.0 to 5.5 V
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