MB86606A Ver la hoja de datos (PDF) - Fujitsu
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MB86606A Datasheet PDF : 64 Pages
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MB86606A
3. 16-Bit Bus Mode – DMA Interface
Pin no.
Pin name I/O
Function
130
DREQ
This is used to output DMA transfer request signals to the
O
DMAC.
DMA data transfer between the SPC and memory is
requested.
129
DACK
This is used to input DMA-enabling signals from the DMAC.
I When the DMA enabling signal is active, DMA reading and
writing are executed.
138, 139, 141 to 144, 1, 3 DMD15 to 8
136
UDMDP
Upper byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O
connected.
When 80-series mode: The 2nd data is input/output.
When 68-series mode: The 1st data is input/output.
4, 5, 7, 9 to 11, 13, 14 DMD7 to 0
15
LDMDP
Lower byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O
connected.
When 80-series mode: The 1st data is input/output.
When 68-series mode: The 2nd data is input/output.
In 80-series mode: This is used to input the IORD or RD
signal for outputting data from the SPC
135
DMRD (DMR/W)
I
to the DMA bus.
In 68-series mode: This is used to input the R/W control
signal for outputting and inputting data
from the DMAC to the SPC.
In 80-series mode: This is used to input the IOWR or WR
signal for inputting data from the DMA
133
DMWR (DMLDS)
I
bus to the SPC.
In 68-series mode: This is used to input the LDS signal
output by the DMAC when the lower
byte of the DMA data bus is valid.
In 80-series mode: This is used to input the BHE signal
output by the DMAC when the upper
132
DMBHE (DMUDS)
I
byte of the DMA data bus is valid.
In 68-series mode: This is used to input the UDS signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
125
DMA0
This is used to input the address data A0 signal output by
I the DMAC in the 80-series mode.
In 68-series mode: Connect to power supply pin (VDD).
This is used to input DMA-transfer-enabling signals.
TP
When the TP signal is active, the SPC performs the DMA
126
(Transfer
I transfer.
permission)
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
11
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