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MAXQ314

Single-Phase Power-Measurement IC with I2C Interface

Maxim Integrated 

Single-Phase Power-Measurement

IC with I2C Interface

I2C BUS CONTROLLER TIMING

(VDVDD = 3.0V to 3.6V, TA = +25NC, unless otherwise noted. Typical values are at VDVDD = 3.3V, TA = +25NC.) (Note 1, Figure 2)

PARAMETER

Serial Clock Frequency

Bus Free Time Between a STOP

and a START Condition

Hold Time (Repeated) START

Condition

Repeated START Condition

Setup Time

STOP Condition Setup Time

Data Hold Time

Data Setup Time

SCL Clock Low Period

SCL Clock High Period

Rise Time of Both SDA and SCL

Signals Receiving

Fall Time of Both SDA and SCL

Signals Receiving

SYMBOL

fSCL

tBUF

CONDITIONS

tHD:STA

tSU:STA

tSU:STO

tHD:DAT

tSU:DAT

tLOW

tHIGH

(Note 3)

tR_I2C (Notes 4, 5)

tF_I2C (Notes 4, 5)

Fall Time of SDA Transmitting

Pulse Width of Spike Suppressed

Capacitive Load for Each Bus

Line

tF_TX

tSP

CB

(Notes 4, 5)

(Note 6)

(Note 5)

MIN

TYP

MAX UNITS

400

kHz

1.3

Fs

0.6

Fs

0.6

Fs

0.6

Fs

0.9

Fs

120

ns

1.3

Fs

0.6

Fs

20 +

0.1CB

300

ns

20 +

0.1CB

300

ns

20 +

0.1CB

250

ns

50

ns

400

pF

Note 1: Specifications guaranteed, but not production tested.

Note 2: All parameters tested at TA = +25NC. Specifications over temperature are guaranteed by design.

Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 4: ISINK P 6mA. tR_I2C and tF_I2C measured between 0.3 x VDVDD and 0.7 x VDVDD.

Note 5: CB = Total capacitance of one bus line in pF.

Note 6: Guaranteed by design. Input filters on the SDA and SCL pins suppress noise spikes less than 50ns.

6   _______________________________________________________________________________________

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