MAXQ314 Ver la hoja de datos (PDF) - Maxim Integrated
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MAXQ314 Datasheet PDF : 16 Pages
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Single-Phase Power-Measurement
IC with I2C Interface
I2C Rate and Resets
The I2C bus is dedicated to communications with the
master device. The master device initiates all communi-
cations. During an I2C transfer, data is transmitted and
received over the serial data line (SDA) with respect to
a serial shift clock (SCL). I2C transfers always start with
Table 1. Slave Address Determination
A2
A1
A0
L
L
L
L
L
Z
L
L
H
L
Z
L
L
Z
Z
L
Z
H
L
H
L
L
H
Z
L
H
H
Z
L
L
Z
L
Z
Z
L
H
Z
Z
L
Z
Z
Z
Z
Z
H
Z
H
L
Z
H
Z
Z
H
H
H
L
L
H
L
Z
H
L
H
H
Z
L
H
Z
Z
H
Z
H
H
H
L
H
H
Z
H
H
H
SLAVE ADDRESS :7
60h (1100 000b)
61h (1100 001b)
62h (1100 010b)
63h (1100 011b)
64h (1100 100b)
65h (1100 101b)
66h (1100 110b)
67h (1100 111b)
68h (1101 000b)
69h (1101 001b)
6Ah (1101 010b)
6Bh (1101 011b)
6Ch (1101 100b)
6Dh (1101 101b)
6Eh (1101 110b)
6Fh (1101 111b)
70h (1110 000b)
71h (1110 001b)
72h (1110 010b)
73h (1110 011b)
74h (1110 100b)
75h (1110 101b)
76h (1110 110b)
77h (1110 111b)
78h (1111 000b)
79h (1111 001b)
7Ah (1111 010b)
the most significant bit and end with the least significant
bit. All I2C transfers are 8 bits in length, followed by an
ACK/NACK bit.
The clock rate used for the I2C interface is determined
by the bus master, but can be at most 400kHz. The
MAXQ314 can hold the SCL line low while processing
commands to delay reception of further data. For fre-
quencies at or below 100kHz, the delay can be transpar-
ent, but at 400kHz delays can be noticeable.
A timeout provision resets the I2C controller if a low level
is detected on the SCL pin for a period of 30ms. The I2C
controller returns to its default state, and the SDA and
SCL pins go their idle state.
I2C Slave Address Generation
The A2, A1, and A0 pins are latched following every
reset and used to construct the 7-bit slave address as
shown in Table 1. The pin states are represented by L for
logic 0, H for logic 1, and Z for high impedance.
I2C Protocol
The I2C protocol supports bus timeout and optionally
packet-error checking. When packet-error checking is
enabled by setting the PECEN bit (DSPCFG.3) to 1, a
packet-error code (PEC) byte is appended at the end
of each transaction. The byte is calculated as CRC-8
checksum, calculated over the entire message including
the address and read/write bit. The polynomial used is
x8 + x2 + x + 1 (the CRC-8-ATM HEC algorithm, initial-
ized to zero).
Commands are read and write, the command code byte
being an address of a register to read/write. Data length
is 2 bytes for most registers, both read and write; 3 bytes
for power (P, Q, S, PAVG), VRMS, and IRMS read com-
mands. The MAXQ314 could be unable to report data
like power, IRMS, VRMS, etc., immediately if the read
command is received while the requested data is being
calculated. In such a case, the clock line is held low
until the calculation completes or a bus timeout occurs.
The firmware does not support ARA address or address
broadcast features.
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